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Searched refs:chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE (Results 1 – 2 of 2) sorted by relevance

/linux-2.6.39/arch/arm/mach-bcmring/include/mach/csp/
DchipcHw_inline.h1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable()
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable()
DchipcHw_reg.h507 #define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ macro