1 #ifndef __ALPHA_T2__H__
2 #define __ALPHA_T2__H__
3 
4 /* Fit everything into one 128MB HAE window. */
5 #define T2_ONE_HAE_WINDOW 1
6 
7 #include <linux/types.h>
8 #include <linux/spinlock.h>
9 #include <asm/compiler.h>
10 #include <asm/system.h>
11 
12 /*
13  * T2 is the internal name for the core logic chipset which provides
14  * memory controller and PCI access for the SABLE-based systems.
15  *
16  * This file is based on:
17  *
18  * SABLE I/O Specification
19  * Revision/Update Information: 1.3
20  *
21  * jestabro@amt.tay1.dec.com Initial Version.
22  *
23  */
24 
25 #define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 27 bits */
26 
27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
28 /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
29 #define _GAMMA_BIAS		0x8000000000UL
30 
31 #if defined(CONFIG_ALPHA_GENERIC)
32 #define GAMMA_BIAS		alpha_mv.sys.t2.gamma_bias
33 #elif defined(CONFIG_ALPHA_GAMMA)
34 #define GAMMA_BIAS		_GAMMA_BIAS
35 #else
36 #define GAMMA_BIAS		0
37 #endif
38 
39 /*
40  * Memory spaces:
41  */
42 #define T2_CONF		        (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
43 #define T2_IO			(IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
44 #define T2_SPARSE_MEM		(IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
45 #define T2_DENSE_MEM	        (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
46 
47 #define T2_IOCSR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
48 #define T2_CERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
49 #define T2_CERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
50 #define T2_CERR3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
51 #define T2_PERR1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
52 #define T2_PERR2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
53 #define T2_PSCR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
54 #define T2_HAE_1		(IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
55 #define T2_HAE_2		(IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
56 #define T2_HBASE		(IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
57 #define T2_WBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
58 #define T2_WMASK1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
59 #define T2_TBASE1		(IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
60 #define T2_WBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
61 #define T2_WMASK2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
62 #define T2_TBASE2		(IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
63 #define T2_TLBBR		(IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
64 #define T2_IVR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
65 #define T2_HAE_3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
66 #define T2_HAE_4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
67 
68 /* The CSRs below are T3/T4 only */
69 #define T2_WBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
70 #define T2_WMASK3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
71 #define T2_TBASE3		(IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
72 
73 #define T2_TDR0			(IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
74 #define T2_TDR1			(IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
75 #define T2_TDR2			(IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
76 #define T2_TDR3			(IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
77 #define T2_TDR4			(IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
78 #define T2_TDR5			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
79 #define T2_TDR6			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
80 #define T2_TDR7			(IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
81 
82 #define T2_WBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
83 #define T2_WMASK4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
84 #define T2_TBASE4		(IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
85 
86 #define T2_AIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
87 #define T2_VAR			(IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
88 #define T2_DIR			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
89 #define T2_ICE			(IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
90 
91 #ifndef T2_ONE_HAE_WINDOW
92 #define T2_HAE_ADDRESS		T2_HAE_1
93 #endif
94 
95 /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
96  3.8fff.ffff
97  *
98  *  +--------------+ 3 8000 0000
99  *  | CPU 0 CSRs   |
100  *  +--------------+ 3 8100 0000
101  *  | CPU 1 CSRs   |
102  *  +--------------+ 3 8200 0000
103  *  | CPU 2 CSRs   |
104  *  +--------------+ 3 8300 0000
105  *  | CPU 3 CSRs   |
106  *  +--------------+ 3 8400 0000
107  *  | CPU Reserved |
108  *  +--------------+ 3 8700 0000
109  *  | Mem Reserved |
110  *  +--------------+ 3 8800 0000
111  *  | Mem 0 CSRs   |
112  *  +--------------+ 3 8900 0000
113  *  | Mem 1 CSRs   |
114  *  +--------------+ 3 8a00 0000
115  *  | Mem 2 CSRs   |
116  *  +--------------+ 3 8b00 0000
117  *  | Mem 3 CSRs   |
118  *  +--------------+ 3 8c00 0000
119  *  | Mem Reserved |
120  *  +--------------+ 3 8e00 0000
121  *  | PCI Bridge   |
122  *  +--------------+ 3 8f00 0000
123  *  | Expansion IO |
124  *  +--------------+ 3 9000 0000
125  *
126  *
127  */
128 #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
129 #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
130 #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
131 #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
132 
133 #define T2_CPUn_BASE(n)		(T2_CPU0_BASE + (((n)&3) * 0x001000000L))
134 
135 #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
136 #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
137 #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
138 #define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
139 
140 
141 /*
142  * Sable CPU Module CSRS
143  *
144  * These are CSRs for hardware other than the CPU chip on the CPU module.
145  * The CPU module has Backup Cache control logic, Cbus control logic, and
146  * interrupt control logic on it.  There is a duplicate tag store to speed
147  * up maintaining cache coherency.
148  */
149 
150 struct sable_cpu_csr {
151   unsigned long bcc;     long fill_00[3]; /* Backup Cache Control */
152   unsigned long bcce;    long fill_01[3]; /* Backup Cache Correctable Error */
153   unsigned long bccea;   long fill_02[3]; /* B-Cache Corr Err Address Latch */
154   unsigned long bcue;    long fill_03[3]; /* B-Cache Uncorrectable Error */
155   unsigned long bcuea;   long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
156   unsigned long dter;    long fill_05[3]; /* Duplicate Tag Error */
157   unsigned long cbctl;   long fill_06[3]; /* CBus Control */
158   unsigned long cbe;     long fill_07[3]; /* CBus Error */
159   unsigned long cbeal;   long fill_08[3]; /* CBus Error Addr Latch low */
160   unsigned long cbeah;   long fill_09[3]; /* CBus Error Addr Latch high */
161   unsigned long pmbx;    long fill_10[3]; /* Processor Mailbox */
162   unsigned long ipir;    long fill_11[3]; /* Inter-Processor Int Request */
163   unsigned long sic;     long fill_12[3]; /* System Interrupt Clear */
164   unsigned long adlk;    long fill_13[3]; /* Address Lock (LDxL/STxC) */
165   unsigned long madrl;   long fill_14[3]; /* CBus Miss Address */
166   unsigned long rev;     long fill_15[3]; /* CMIC Revision */
167 };
168 
169 /*
170  * Data structure for handling T2 machine checks:
171  */
172 struct el_t2_frame_header {
173 	unsigned int	elcf_fid;	/* Frame ID (from above) */
174 	unsigned int	elcf_size;	/* Size of frame in bytes */
175 };
176 
177 struct el_t2_procdata_mcheck {
178 	unsigned long	elfmc_paltemp[32];	/* PAL TEMP REGS. */
179 	/* EV4-specific fields */
180 	unsigned long	elfmc_exc_addr;	/* Addr of excepting insn. */
181 	unsigned long	elfmc_exc_sum;	/* Summary of arith traps. */
182 	unsigned long	elfmc_exc_mask;	/* Exception mask (from exc_sum). */
183 	unsigned long	elfmc_iccsr;	/* IBox hardware enables. */
184 	unsigned long	elfmc_pal_base;	/* Base address for PALcode. */
185 	unsigned long	elfmc_hier;	/* Hardware Interrupt Enable. */
186 	unsigned long	elfmc_hirr;	/* Hardware Interrupt Request. */
187 	unsigned long	elfmc_mm_csr;	/* D-stream fault info. */
188 	unsigned long	elfmc_dc_stat;	/* D-cache status (ECC/Parity Err). */
189 	unsigned long	elfmc_dc_addr;	/* EV3 Phys Addr for ECC/DPERR. */
190 	unsigned long	elfmc_abox_ctl;	/* ABox Control Register. */
191 	unsigned long	elfmc_biu_stat;	/* BIU Status. */
192 	unsigned long	elfmc_biu_addr;	/* BUI Address. */
193 	unsigned long	elfmc_biu_ctl;	/* BIU Control. */
194 	unsigned long	elfmc_fill_syndrome; /* For correcting ECC errors. */
195 	unsigned long	elfmc_fill_addr;/* Cache block which was being read. */
196 	unsigned long	elfmc_va;	/* Effective VA of fault or miss. */
197 	unsigned long	elfmc_bc_tag;	/* Backup Cache Tag Probe Results. */
198 };
199 
200 /*
201  * Sable processor specific Machine Check Data segment.
202  */
203 
204 struct el_t2_logout_header {
205 	unsigned int	elfl_size;	/* size in bytes of logout area. */
206 	unsigned int	elfl_sbz1:31;	/* Should be zero. */
207 	unsigned int	elfl_retry:1;	/* Retry flag. */
208 	unsigned int	elfl_procoffset; /* Processor-specific offset. */
209 	unsigned int	elfl_sysoffset;	 /* Offset of system-specific. */
210 	unsigned int	elfl_error_type;	/* PAL error type code. */
211 	unsigned int	elfl_frame_rev;		/* PAL Frame revision. */
212 };
213 struct el_t2_sysdata_mcheck {
214 	unsigned long    elcmc_bcc;	      /* CSR 0 */
215 	unsigned long    elcmc_bcce;	      /* CSR 1 */
216 	unsigned long    elcmc_bccea;      /* CSR 2 */
217 	unsigned long    elcmc_bcue;	      /* CSR 3 */
218 	unsigned long    elcmc_bcuea;      /* CSR 4 */
219 	unsigned long    elcmc_dter;	      /* CSR 5 */
220 	unsigned long    elcmc_cbctl;      /* CSR 6 */
221 	unsigned long    elcmc_cbe;	      /* CSR 7 */
222 	unsigned long    elcmc_cbeal;      /* CSR 8 */
223 	unsigned long    elcmc_cbeah;      /* CSR 9 */
224 	unsigned long    elcmc_pmbx;	      /* CSR 10 */
225 	unsigned long    elcmc_ipir;	      /* CSR 11 */
226 	unsigned long    elcmc_sic;	      /* CSR 12 */
227 	unsigned long    elcmc_adlk;	      /* CSR 13 */
228 	unsigned long    elcmc_madrl;      /* CSR 14 */
229 	unsigned long    elcmc_crrev4;     /* CSR 15 */
230 };
231 
232 /*
233  * Sable memory error frame - sable pfms section 3.42
234  */
235 struct el_t2_data_memory {
236 	struct	el_t2_frame_header elcm_hdr;	/* ID$MEM-FERR = 0x08 */
237 	unsigned int  elcm_module;	/* Module id. */
238 	unsigned int  elcm_res04;	/* Reserved. */
239 	unsigned long elcm_merr;	/* CSR0: Error Reg 1. */
240 	unsigned long elcm_mcmd1;	/* CSR1: Command Trap 1. */
241 	unsigned long elcm_mcmd2;	/* CSR2: Command Trap 2. */
242 	unsigned long elcm_mconf;	/* CSR3: Configuration. */
243 	unsigned long elcm_medc1;	/* CSR4: EDC Status 1. */
244 	unsigned long elcm_medc2;	/* CSR5: EDC Status 2. */
245 	unsigned long elcm_medcc;	/* CSR6: EDC Control. */
246 	unsigned long elcm_msctl;	/* CSR7: Stream Buffer Control. */
247 	unsigned long elcm_mref;	/* CSR8: Refresh Control. */
248 	unsigned long elcm_filter;	/* CSR9: CRD Filter Control. */
249 };
250 
251 
252 /*
253  * Sable other CPU error frame - sable pfms section 3.43
254  */
255 struct el_t2_data_other_cpu {
256 	short	      elco_cpuid;	/* CPU ID */
257 	short	      elco_res02[3];
258 	unsigned long elco_bcc;	/* CSR 0 */
259 	unsigned long elco_bcce;	/* CSR 1 */
260 	unsigned long elco_bccea;	/* CSR 2 */
261 	unsigned long elco_bcue;	/* CSR 3 */
262 	unsigned long elco_bcuea;	/* CSR 4 */
263 	unsigned long elco_dter;	/* CSR 5 */
264 	unsigned long elco_cbctl;	/* CSR 6 */
265 	unsigned long elco_cbe;	/* CSR 7 */
266 	unsigned long elco_cbeal;	/* CSR 8 */
267 	unsigned long elco_cbeah;	/* CSR 9 */
268 	unsigned long elco_pmbx;	/* CSR 10 */
269 	unsigned long elco_ipir;	/* CSR 11 */
270 	unsigned long elco_sic;	/* CSR 12 */
271 	unsigned long elco_adlk;	/* CSR 13 */
272 	unsigned long elco_madrl;	/* CSR 14 */
273 	unsigned long elco_crrev4;	/* CSR 15 */
274 };
275 
276 /*
277  * Sable other CPU error frame - sable pfms section 3.44
278  */
279 struct el_t2_data_t2{
280 	struct el_t2_frame_header elct_hdr;	/* ID$T2-FRAME */
281 	unsigned long elct_iocsr;	/* IO Control and Status Register */
282 	unsigned long elct_cerr1;	/* Cbus Error Register 1 */
283 	unsigned long elct_cerr2;	/* Cbus Error Register 2 */
284 	unsigned long elct_cerr3;	/* Cbus Error Register 3 */
285 	unsigned long elct_perr1;	/* PCI Error Register 1 */
286 	unsigned long elct_perr2;	/* PCI Error Register 2 */
287 	unsigned long elct_hae0_1;	/* High Address Extension Register 1 */
288 	unsigned long elct_hae0_2;	/* High Address Extension Register 2 */
289 	unsigned long elct_hbase;	/* High Base Register */
290 	unsigned long elct_wbase1;	/* Window Base Register 1 */
291 	unsigned long elct_wmask1;	/* Window Mask Register 1 */
292 	unsigned long elct_tbase1;	/* Translated Base Register 1 */
293 	unsigned long elct_wbase2;	/* Window Base Register 2 */
294 	unsigned long elct_wmask2;	/* Window Mask Register 2 */
295 	unsigned long elct_tbase2;	/* Translated Base Register 2 */
296 	unsigned long elct_tdr0;	/* TLB Data Register 0 */
297 	unsigned long elct_tdr1;	/* TLB Data Register 1 */
298 	unsigned long elct_tdr2;	/* TLB Data Register 2 */
299 	unsigned long elct_tdr3;	/* TLB Data Register 3 */
300 	unsigned long elct_tdr4;	/* TLB Data Register 4 */
301 	unsigned long elct_tdr5;	/* TLB Data Register 5 */
302 	unsigned long elct_tdr6;	/* TLB Data Register 6 */
303 	unsigned long elct_tdr7;	/* TLB Data Register 7 */
304 };
305 
306 /*
307  * Sable error log data structure - sable pfms section 3.40
308  */
309 struct el_t2_data_corrected {
310 	unsigned long elcpb_biu_stat;
311 	unsigned long elcpb_biu_addr;
312 	unsigned long elcpb_biu_ctl;
313 	unsigned long elcpb_fill_syndrome;
314 	unsigned long elcpb_fill_addr;
315 	unsigned long elcpb_bc_tag;
316 };
317 
318 /*
319  * Sable error log data structure
320  * Note there are 4 memory slots on sable (see t2.h)
321  */
322 struct el_t2_frame_mcheck {
323 	struct el_t2_frame_header elfmc_header;	/* ID$P-FRAME_MCHECK */
324 	struct el_t2_logout_header elfmc_hdr;
325 	struct el_t2_procdata_mcheck elfmc_procdata;
326 	struct el_t2_sysdata_mcheck elfmc_sysdata;
327 	struct el_t2_data_t2 elfmc_t2data;
328 	struct el_t2_data_memory elfmc_memdata[4];
329 	struct el_t2_frame_header elfmc_footer;	/* empty */
330 };
331 
332 
333 /*
334  * Sable error log data structures on memory errors
335  */
336 struct el_t2_frame_corrected {
337 	struct el_t2_frame_header elfcc_header;	/* ID$P-BC-COR */
338 	struct el_t2_logout_header elfcc_hdr;
339 	struct el_t2_data_corrected elfcc_procdata;
340 /*	struct el_t2_data_t2 elfcc_t2data;		*/
341 /*	struct el_t2_data_memory elfcc_memdata[4];	*/
342 	struct el_t2_frame_header elfcc_footer;	/* empty */
343 };
344 
345 
346 #ifdef __KERNEL__
347 
348 #ifndef __EXTERN_INLINE
349 #define __EXTERN_INLINE extern inline
350 #define __IO_EXTERN_INLINE
351 #endif
352 
353 /*
354  * I/O functions:
355  *
356  * T2 (the core logic PCI/memory support chipset for the SABLE
357  * series of processors uses a sparse address mapping scheme to
358  * get at PCI memory and I/O.
359  */
360 
361 #define vip	volatile int *
362 #define vuip	volatile unsigned int *
363 
t2_inb(unsigned long addr)364 extern inline u8 t2_inb(unsigned long addr)
365 {
366 	long result = *(vip) ((addr << 5) + T2_IO + 0x00);
367 	return __kernel_extbl(result, addr & 3);
368 }
369 
t2_outb(u8 b,unsigned long addr)370 extern inline void t2_outb(u8 b, unsigned long addr)
371 {
372 	unsigned long w;
373 
374 	w = __kernel_insbl(b, addr & 3);
375 	*(vuip) ((addr << 5) + T2_IO + 0x00) = w;
376 	mb();
377 }
378 
t2_inw(unsigned long addr)379 extern inline u16 t2_inw(unsigned long addr)
380 {
381 	long result = *(vip) ((addr << 5) + T2_IO + 0x08);
382 	return __kernel_extwl(result, addr & 3);
383 }
384 
t2_outw(u16 b,unsigned long addr)385 extern inline void t2_outw(u16 b, unsigned long addr)
386 {
387 	unsigned long w;
388 
389 	w = __kernel_inswl(b, addr & 3);
390 	*(vuip) ((addr << 5) + T2_IO + 0x08) = w;
391 	mb();
392 }
393 
t2_inl(unsigned long addr)394 extern inline u32 t2_inl(unsigned long addr)
395 {
396 	return *(vuip) ((addr << 5) + T2_IO + 0x18);
397 }
398 
t2_outl(u32 b,unsigned long addr)399 extern inline void t2_outl(u32 b, unsigned long addr)
400 {
401 	*(vuip) ((addr << 5) + T2_IO + 0x18) = b;
402 	mb();
403 }
404 
405 
406 /*
407  * Memory functions.
408  *
409  * For reading and writing 8 and 16 bit quantities we need to
410  * go through one of the three sparse address mapping regions
411  * and use the HAE_MEM CSR to provide some bits of the address.
412  * The following few routines use only sparse address region 1
413  * which gives 1Gbyte of accessible space which relates exactly
414  * to the amount of PCI memory mapping *into* system address space.
415  * See p 6-17 of the specification but it looks something like this:
416  *
417  * 21164 Address:
418  *
419  *          3         2         1
420  * 9876543210987654321098765432109876543210
421  * 1ZZZZ0.PCI.QW.Address............BBLL
422  *
423  * ZZ = SBZ
424  * BB = Byte offset
425  * LL = Transfer length
426  *
427  * PCI Address:
428  *
429  * 3         2         1
430  * 10987654321098765432109876543210
431  * HHH....PCI.QW.Address........ 00
432  *
433  * HHH = 31:29 HAE_MEM CSR
434  *
435  */
436 
437 #ifdef T2_ONE_HAE_WINDOW
438 #define t2_set_hae
439 #else
440 #define t2_set_hae { \
441 	unsigned long msb = addr >> 27; \
442 	addr &= T2_MEM_R1_MASK; \
443 	set_hae(msb); \
444 }
445 #endif
446 
447 /*
448  * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since
449  *       they may be called directly, rather than through the
450  *       ioreadNN/iowriteNN routines.
451  */
452 
t2_readb(const volatile void __iomem * xaddr)453 __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
454 {
455 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
456 	unsigned long result;
457 
458 	t2_set_hae;
459 
460 	result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
461 	return __kernel_extbl(result, addr & 3);
462 }
463 
t2_readw(const volatile void __iomem * xaddr)464 __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
465 {
466 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
467 	unsigned long result;
468 
469 	t2_set_hae;
470 
471 	result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
472 	return __kernel_extwl(result, addr & 3);
473 }
474 
475 /*
476  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
477  * because we cannot access all of DENSE without changing its HAE.
478  */
t2_readl(const volatile void __iomem * xaddr)479 __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
480 {
481 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
482 	unsigned long result;
483 
484 	t2_set_hae;
485 
486 	result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
487 	return result & 0xffffffffUL;
488 }
489 
t2_readq(const volatile void __iomem * xaddr)490 __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
491 {
492 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
493 	unsigned long r0, r1, work;
494 
495 	t2_set_hae;
496 
497 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
498 	r0 = *(vuip)(work);
499 	r1 = *(vuip)(work + (4 << 5));
500 	return r1 << 32 | r0;
501 }
502 
t2_writeb(u8 b,volatile void __iomem * xaddr)503 __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
504 {
505 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
506 	unsigned long w;
507 
508 	t2_set_hae;
509 
510 	w = __kernel_insbl(b, addr & 3);
511 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
512 }
513 
t2_writew(u16 b,volatile void __iomem * xaddr)514 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
515 {
516 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
517 	unsigned long w;
518 
519 	t2_set_hae;
520 
521 	w = __kernel_inswl(b, addr & 3);
522 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
523 }
524 
525 /*
526  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
527  * because we cannot access all of DENSE without changing its HAE.
528  */
t2_writel(u32 b,volatile void __iomem * xaddr)529 __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
530 {
531 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
532 
533 	t2_set_hae;
534 
535 	*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
536 }
537 
t2_writeq(u64 b,volatile void __iomem * xaddr)538 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
539 {
540 	unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
541 	unsigned long work;
542 
543 	t2_set_hae;
544 
545 	work = (addr << 5) + T2_SPARSE_MEM + 0x18;
546 	*(vuip)work = b;
547 	*(vuip)(work + (4 << 5)) = b >> 32;
548 }
549 
t2_ioportmap(unsigned long addr)550 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
551 {
552 	return (void __iomem *)(addr + T2_IO);
553 }
554 
t2_ioremap(unsigned long addr,unsigned long size)555 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr,
556 					 unsigned long size)
557 {
558 	return (void __iomem *)(addr + T2_DENSE_MEM);
559 }
560 
t2_is_ioaddr(unsigned long addr)561 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
562 {
563 	return (long)addr >= 0;
564 }
565 
t2_is_mmio(const volatile void __iomem * addr)566 __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
567 {
568 	return (unsigned long)addr >= T2_DENSE_MEM;
569 }
570 
571 /* New-style ioread interface.  The mmio routines are so ugly for T2 that
572    it doesn't make sense to merge the pio and mmio routines.  */
573 
574 #define IOPORT(OS, NS)							\
575 __EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr)		\
576 {									\
577 	if (t2_is_mmio(xaddr))						\
578 		return t2_read##OS(xaddr);				\
579 	else								\
580 		return t2_in##OS((unsigned long)xaddr - T2_IO);		\
581 }									\
582 __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr)	\
583 {									\
584 	if (t2_is_mmio(xaddr))						\
585 		t2_write##OS(b, xaddr);					\
586 	else								\
587 		t2_out##OS(b, (unsigned long)xaddr - T2_IO);		\
588 }
589 
590 IOPORT(b, 8)
591 IOPORT(w, 16)
592 IOPORT(l, 32)
593 
594 #undef IOPORT
595 
596 #undef vip
597 #undef vuip
598 
599 #undef __IO_PREFIX
600 #define __IO_PREFIX		t2
601 #define t2_trivial_rw_bw	0
602 #define t2_trivial_rw_lq	0
603 #define t2_trivial_io_bw	0
604 #define t2_trivial_io_lq	0
605 #define t2_trivial_iounmap	1
606 #include <asm/io_trivial.h>
607 
608 #ifdef __IO_EXTERN_INLINE
609 #undef __EXTERN_INLINE
610 #undef __IO_EXTERN_INLINE
611 #endif
612 
613 #endif /* __KERNEL__ */
614 
615 #endif /* __ALPHA_T2__H__ */
616