Searched refs:acpibase (Results 1 – 3 of 3) sorted by relevance
38 #define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */39 #define TCOBASE (acpibase + 0x60) /* TCO base address */84 static void supermicro_old_pre_start(unsigned long acpibase) in supermicro_old_pre_start() argument94 static void supermicro_old_pre_stop(unsigned long acpibase) in supermicro_old_pre_stop() argument272 static void broken_bios_start(unsigned long acpibase) in broken_bios_start() argument283 static void broken_bios_stop(unsigned long acpibase) in broken_bios_stop() argument298 void iTCO_vendor_pre_start(unsigned long acpibase, in iTCO_vendor_pre_start() argument303 supermicro_old_pre_start(acpibase); in iTCO_vendor_pre_start()309 broken_bios_start(acpibase); in iTCO_vendor_pre_start()315 void iTCO_vendor_pre_stop(unsigned long acpibase) in iTCO_vendor_pre_stop() argument[all …]
9 #define iTCO_vendor_pre_start(acpibase, heartbeat) {} argument10 #define iTCO_vendor_pre_stop(acpibase) {} argument11 #define iTCO_vendor_pre_keepalive(acpibase, heartbeat) {} argument
913 unsigned int acpibase; in SiS_SetChrontelGPIO() local918 acpibase = sisfb_read_lpc_pci_dword(SiS_Pr, 0x74); in SiS_SetChrontelGPIO()919 acpibase &= 0xFFFF; in SiS_SetChrontelGPIO()920 if(!acpibase) return; in SiS_SetChrontelGPIO()921 temp = SiS_GetRegShort((acpibase + 0x3c)); /* ACPI register 0x3c: GP Event 1 I/O mode select */ in SiS_SetChrontelGPIO()923 SiS_SetRegShort((acpibase + 0x3c), temp); in SiS_SetChrontelGPIO()924 temp = SiS_GetRegShort((acpibase + 0x3c)); in SiS_SetChrontelGPIO()925 temp = SiS_GetRegShort((acpibase + 0x3a)); /* ACPI register 0x3a: GP Pin Level (low/high) */ in SiS_SetChrontelGPIO()928 SiS_SetRegShort((acpibase + 0x3a), temp); in SiS_SetChrontelGPIO()929 temp = SiS_GetRegShort((acpibase + 0x3a)); in SiS_SetChrontelGPIO()