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Searched refs:__REG (Results 1 – 25 of 25) sorted by relevance

/linux-2.6.39/arch/arm/mach-pxa/include/mach/
Dpxa27x-udc.h8 #define UDCCR __REG(0x40600000) /* UDC Control Register */
32 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
47 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
56 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
84 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
103 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
[all …]
Dregs-uart.h10 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
12 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
13 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
15 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
16 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
17 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
19 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
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Dpxa2xx-regs.h23 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
24 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
25 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
26 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
27 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
28 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
29 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
30 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
31 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
32 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
[all …]
Dpxa25x-udc.h8 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
12 #define UDCCR __REG(0x40600000) /* UDC Control Register */
22 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
33 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
46 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
[all …]
Dpxa3xx-regs.h21 #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
29 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
30 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
31 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
32 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
33 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
34 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
35 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
36 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
37 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
[all …]
Dregs-intc.h10 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
11 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
12 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
13 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
16 #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
18 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
19 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
20 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
[all …]
Dregs-ac97.h10 #define POCR __REG(0x40500000) /* PCM Out Control Register */
14 #define PICR __REG(0x40500004) /* PCM In Control Register */
18 #define MCCR __REG(0x40500008) /* Mic In Control Register */
22 #define GCR __REG(0x4050000C) /* Global Control Register */
38 #define POSR __REG(0x40500010) /* PCM Out Status Register */
42 #define PISR __REG(0x40500014) /* PCM In Status Register */
47 #define MCSR __REG(0x40500018) /* Mic In Status Register */
52 #define GSR __REG(0x4050001C) /* Global Status Register */
71 #define CAR __REG(0x40500020) /* CODEC Access Register */
74 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
[all …]
Dregs-ost.h10 #define OSMR0 __REG(0x40A00000) /* */
11 #define OSMR1 __REG(0x40A00004) /* */
12 #define OSMR2 __REG(0x40A00008) /* */
13 #define OSMR3 __REG(0x40A0000C) /* */
14 #define OSMR4 __REG(0x40A00080) /* */
15 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
16 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
17 #define OMCR4 __REG(0x40A000C0) /* */
18 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
19 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
[all …]
Dregs-rtc.h10 #define RCNR __REG(0x40900000) /* RTC Count Register */
11 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
12 #define RTSR __REG(0x40900008) /* RTC Status Register */
13 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
14 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
Dhardware.h44 # define __REG(x) (*((volatile u32 *)io_p2v(x))) macro
49 (*(volatile u32 *)((u32)&__REG(x) + (y)))
55 # define __REG(x) io_p2v(x) macro
Dpxa27x.h8 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/linux-2.6.39/arch/arm/mach-ns9xxx/include/mach/
Dregs-mem.h19 #define MEM_CTRL __REG(0xa0700000)
22 #define MEM_STAT __REG(0xa0700004)
25 #define MEM_CONF __REG(0xa0700008)
28 #define MEM_DMCTRL __REG(0xa0700020)
31 #define MEM_DMRT __REG(0xa0700024)
34 #define MEM_DMRC __REG(0xa0700028)
37 #define MEM_DMPCP __REG(0xa0700030)
40 #define MEM_DMAPCP __REG(0xa0700034)
43 #define MEM_DMSRET __REG(0xa0700038)
46 #define MEM_DMLDOAT __REG(0xa070003c)
[all …]
Duncompress.h16 #define __REG(x) ((void __iomem __force *)(x)) macro
68 #define MSCS __REG(0xA0900184)
70 #define NS9360_UARTA __REG(0x90200040)
71 #define NS9360_UARTB __REG(0x90200000)
72 #define NS9360_UARTC __REG(0x90300000)
73 #define NS9360_UARTD __REG(0x90300040)
78 #define A9M9750DEV_UARTA __REG(0x40000000)
80 #define NS921XSYS_CLOCK __REG(0xa090017c)
81 #define NS921X_UARTA __REG(0x90010000)
82 #define NS921X_UARTB __REG(0x90018000)
[all …]
Dregs-bbu.h37 #define BBU_GCTRL1 __REG(0x90600030)
38 #define BBU_GCTRL2 __REG(0x90600034)
39 #define BBU_GCTRL3 __REG(0x90600120)
41 #define BBU_GSTAT1 __REG(0x90600040)
42 #define BBU_GSTAT2 __REG(0x90600044)
43 #define BBU_GSTAT3 __REG(0x90600130)
Dregs-sys-common.h23 #define SYS_ISRADDR __REG(0xa0900164)
26 #define SYS_ISA __REG(0xa0900168)
29 #define SYS_ISR __REG(0xa090016c)
Dregs-sys-ns9360.h19 #define SYS_AHBAGENCONF __REG(0xa0900000)
31 #define SYS_TIS __REG(0xa0900170)
34 #define SYS_PLL __REG(0xa0900188)
127 #define SYS_GENID __REG(0xa0900210)
Dregs-board-a9m9750dev.h21 #define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22 #define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
Dhardware.h36 # define __REG(x) ((void __iomem __force *)io_p2v((x))) macro
72 # define __REG(x) io_p2v(x) macro
/linux-2.6.39/arch/arm/mach-sa1100/include/mach/
DSA-1100.h110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
[all …]
Dhardware.h59 # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) macro
68 # define __REG(x) io_p2v(x) macro
/linux-2.6.39/arch/arm/plat-tcc/include/mach/
Dtcc8k-regs.h41 #define __REG(x) (*((volatile u32 *)(x))) macro
374 #define PIC0_IEN __REG(PIC0_BASE + PIC0_IEN_OFFS)
375 #define PIC0_IEN_PHYS __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS)
376 #define PIC0_CREQ __REG(PIC0_BASE + PIC0_CREQ_OFFS)
377 #define PIC0_CREQ_PHYS __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS)
378 #define PIC0_IREQ __REG(PIC0_BASE + PIC0_IREQ_OFFS)
379 #define PIC0_IRQSEL __REG(PIC0_BASE + PIC0_IRQSEL_OFFS)
380 #define PIC0_IRQSEL_PHYS __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS)
381 #define PIC0_SRC __REG(PIC0_BASE + PIC0_SRC_OFFS)
382 #define PIC0_MREQ __REG(PIC0_BASE + PIC0_MREQ_OFFS)
[all …]
/linux-2.6.39/sound/soc/pxa/
Dpxa2xx-i2s.c35 #define SACR0 __REG(0x40400000) /* Global Control Register */
36 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
37 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Reg…
38 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
39 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
40 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
41 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
/linux-2.6.39/drivers/net/irda/
Dpxaficp_ir.c33 #define FICP __REG(0x40800000) /* Start of FICP area */
34 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
35 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
36 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
37 #define ICDR __REG(0x4080000c) /* ICP Data Register */
38 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
39 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
/linux-2.6.39/arch/arm/mach-dove/include/mach/
Dhardware.h22 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ macro
/linux-2.6.39/arch/xtensa/include/asm/
Dcoprocessor.h117 __REG ## list (cc, abi, type, name, size, align)