1 //--------------------------------------------------------------------------- 2 // FT1000 driver for Flarion Flash OFDM NIC Device 3 // 4 // Copyright (C) 2002 Flarion Technologies, All rights reserved. 5 // 6 // This program is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License as published by the Free 8 // Software Foundation; either version 2 of the License, or (at your option) any 9 // later version. This program is distributed in the hope that it will be useful, 10 // but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 // more details. You should have received a copy of the GNU General Public 13 // License along with this program; if not, write to the 14 // Free Software Foundation, Inc., 59 Temple Place - 15 // Suite 330, Boston, MA 02111-1307, USA. 16 //--------------------------------------------------------------------------- 17 // 18 // File: ft1000.h 19 // 20 // Description: Common structures and defines 21 // 22 // History: 23 // 8/29/02 Whc Ported to Linux. 24 // 7/19/04 Whc Drop packet and cmd msg with pseudo header 25 // checksum 26 // 10/27/04 Whc Added dynamic downloading of test image. 27 // 01/11/04 Whc Added support for Magnemite ASIC 28 // 29 //--------------------------------------------------------------------------- 30 #ifndef _FT1000H_ 31 #define _FT1000H_ 32 33 34 #define FT1000_DRV_VER 0x01010300 35 36 #define DSPVERSZ 4 37 #define HWSERNUMSZ 16 38 #define SKUSZ 20 39 #define EUISZ 8 40 #define MODESZ 2 41 #define CALVERSZ 2 42 #define CALDATESZ 6 43 44 // Pseudo Header structure 45 typedef struct _PSEUDO_HDR 46 { 47 unsigned short length; // length of msg body 48 unsigned char source; // hardware source id 49 // Host = 0x10 50 // Dsp = 0x20 51 unsigned char destination; // hardware destination id (refer to source) 52 unsigned char portdest; // software destination port id 53 // Host = 0x00 54 // Applicaton Broadcast = 0x10 55 // Network Stack = 0x20 56 // Dsp OAM = 0x80 57 // Dsp Airlink = 0x90 58 // Dsp Loader = 0xa0 59 // Dsp MIP = 0xb0 60 unsigned char portsrc; // software source port id (refer to portdest) 61 unsigned short sh_str_id; // not used 62 unsigned char control; // not used 63 unsigned char rsvd1; 64 unsigned char seq_num; // message sequence number 65 unsigned char rsvd2; 66 unsigned short qos_class; // not used 67 unsigned short checksum; // pseudo header checksum 68 } __attribute__ ((packed)) PSEUDO_HDR, *PPSEUDO_HDR; 69 70 // Definitions to maintain compatibility between other platforms 71 #define UCHAR u8 72 #define USHORT u16 73 #define ULONG u32 74 #define BOOLEAN u8 75 #define PULONG u32 * 76 #define PUSHORT u16 * 77 #define PUCHAR u8 * 78 #define PCHAR u8 * 79 #define UINT u32 80 81 #define ELECTRABUZZ_ID 0 // ASIC ID for Electrabuzz 82 #define MAGNEMITE_ID 0x1a01 // ASIC ID for Magnemite 83 84 // MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE 85 #define FT1000_REG_DPRAM_ADDR 0x000E // DPADR - Dual Port Ram Indirect Address Register 86 #define FT1000_REG_SUP_CTRL 0x0020 // HCTR - Host Control Register 87 #define FT1000_REG_SUP_STAT 0x0022 // HSTAT - Host Status Register 88 #define FT1000_REG_RESET 0x0024 // HCTR - Host Control Register 89 #define FT1000_REG_SUP_ISR 0x0026 // HISR - Host Interrupt Status Register 90 #define FT1000_REG_SUP_IMASK 0x0028 // HIMASK - Host Interrupt Mask 91 #define FT1000_REG_DOORBELL 0x002a // DBELL - Door Bell Register 92 #define FT1000_REG_ASIC_ID 0x002e // ASICID - ASIC Identification Number 93 // (Electrabuzz=0 Magnemite=0x1A01) 94 95 // MEMORY MAP FOR ELECTRABUZZ ASIC 96 97 #define FT1000_REG_UFIFO_STAT 0x0000 // UFSR - Uplink FIFO status register 98 #define FT1000_REG_UFIFO_BEG 0x0002 // UFBR - Uplink FIFO beginning register 99 #define FT1000_REG_UFIFO_MID 0x0004 // UFMR - Uplink FIFO middle register 100 #define FT1000_REG_UFIFO_END 0x0006 // UFER - Uplink FIFO end register 101 #define FT1000_REG_DFIFO_STAT 0x0008 // DFSR - Downlink FIFO status register 102 #define FT1000_REG_DFIFO 0x000A // DFR - Downlink FIFO Register 103 #define FT1000_REG_DPRAM_DATA 0x000C // DPRAM - Dual Port Indirect Data Register 104 #define FT1000_REG_WATERMARK 0x0010 // WMARK - Watermark Register 105 106 // MEMORY MAP FOR MAGNEMITE 107 #define FT1000_REG_MAG_UFDR 0x0000 // UFDR - Uplink FIFO Data Register (32-bits) 108 #define FT1000_REG_MAG_UFDRL 0x0000 // UFDRL - Uplink FIFO Data Register low-word (16-bits) 109 #define FT1000_REG_MAG_UFDRH 0x0002 // UFDRH - Uplink FIFO Data Register high-word (16-bits) 110 #define FT1000_REG_MAG_UFER 0x0004 // UFER - Uplink FIFO End Register 111 #define FT1000_REG_MAG_UFSR 0x0006 // UFSR - Uplink FIFO Status Register 112 #define FT1000_REG_MAG_DFR 0x0008 // DFR - Downlink FIFO Register (32-bits) 113 #define FT1000_REG_MAG_DFRL 0x0008 // DFRL - Downlink FIFO Register low-word (16-bits) 114 #define FT1000_REG_MAG_DFRH 0x000a // DFRH - Downlink FIFO Register high-word (16-bits) 115 #define FT1000_REG_MAG_DFSR 0x000c // DFSR - Downlink FIFO Status Register 116 #define FT1000_REG_MAG_DPDATA 0x0010 // DPDATA - Dual Port RAM Indirect Data Register (32-bits) 117 #define FT1000_REG_MAG_DPDATAL 0x0010 // DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits) 118 #define FT1000_REG_MAG_DPDATAH 0x0012 // DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits) 119 #define FT1000_REG_MAG_WATERMARK 0x002c // WMARK - Watermark Register 120 121 // Reserved Dual Port RAM offsets for Electrabuzz 122 #define FT1000_DPRAM_TX_BASE 0x0002 // Host to PC Card Messaging Area 123 #define FT1000_DPRAM_RX_BASE 0x0800 // PC Card to Host Messaging Area 124 #define FT1000_FIFO_LEN 0x7FC // total length for DSP FIFO tracking 125 #define FT1000_HI_HO 0x7FE // heartbeat with HI/HO 126 #define FT1000_DSP_STATUS 0xFFE // dsp status - non-zero is a request to reset dsp 127 #define FT1000_DSP_LED 0xFFA // dsp led status for PAD device 128 #define FT1000_DSP_CON_STATE 0xFF8 // DSP Connection Status Info 129 #define FT1000_DPRAM_FEFE 0x002 // location for dsp ready indicator 130 #define FT1000_DSP_TIMER0 0x1FF0 // Timer Field from Basestation 131 #define FT1000_DSP_TIMER1 0x1FF2 // Timer Field from Basestation 132 #define FT1000_DSP_TIMER2 0x1FF4 // Timer Field from Basestation 133 #define FT1000_DSP_TIMER3 0x1FF6 // Timer Field from Basestation 134 135 // Reserved Dual Port RAM offsets for Magnemite 136 #define FT1000_DPRAM_MAG_TX_BASE 0x0000 // Host to PC Card Messaging Area 137 #define FT1000_DPRAM_MAG_RX_BASE 0x0200 // PC Card to Host Messaging Area 138 #define FT1000_MAG_FIFO_LEN 0x1FF // total length for DSP FIFO tracking 139 #define FT1000_MAG_FIFO_LEN_INDX 0x1 // low-word index 140 #define FT1000_MAG_HI_HO 0x1FF // heartbeat with HI/HO 141 #define FT1000_MAG_HI_HO_INDX 0x0 // high-word index 142 #define FT1000_MAG_DSP_LED 0x3FE // dsp led status for PAD device 143 #define FT1000_MAG_DSP_LED_INDX 0x0 // dsp led status for PAD device 144 145 #define FT1000_MAG_DSP_CON_STATE 0x3FE // DSP Connection Status Info 146 #define FT1000_MAG_DSP_CON_STATE_INDX 0x1 // DSP Connection Status Info 147 148 #define FT1000_MAG_DPRAM_FEFE 0x000 // location for dsp ready indicator 149 #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 // location for dsp ready indicator 150 151 #define FT1000_MAG_DSP_TIMER0 0x3FC // Timer Field from Basestation 152 #define FT1000_MAG_DSP_TIMER0_INDX 0x1 153 154 #define FT1000_MAG_DSP_TIMER1 0x3FC // Timer Field from Basestation 155 #define FT1000_MAG_DSP_TIMER1_INDX 0x0 156 157 #define FT1000_MAG_DSP_TIMER2 0x3FD // Timer Field from Basestation 158 #define FT1000_MAG_DSP_TIMER2_INDX 0x1 159 160 #define FT1000_MAG_DSP_TIMER3 0x3FD // Timer Field from Basestation 161 #define FT1000_MAG_DSP_TIMER3_INDX 0x0 162 163 #define FT1000_MAG_TOTAL_LEN 0x200 164 #define FT1000_MAG_TOTAL_LEN_INDX 0x1 165 166 #define FT1000_MAG_PH_LEN 0x200 167 #define FT1000_MAG_PH_LEN_INDX 0x0 168 169 #define FT1000_MAG_PORT_ID 0x201 170 #define FT1000_MAG_PORT_ID_INDX 0x0 171 172 #define HOST_INTF_LE 0x0 // Host interface little endian mode 173 #define HOST_INTF_BE 0x1 // Host interface big endian mode 174 175 // PC Card to Host Doorbell assignments 176 #define FT1000_DB_DPRAM_RX 0x0001 // this value indicates that DSP has 177 // data for host in DPRAM 178 #define FT1000_ASIC_RESET_REQ 0x0004 // DSP requesting host to reset the ASIC 179 #define FT1000_DSP_ASIC_RESET 0x0008 // DSP indicating host that it will reset the ASIC 180 #define FT1000_DB_COND_RESET 0x0010 // DSP request for a card reset. 181 182 // Host to PC Card Doorbell assignments 183 #define FT1000_DB_DPRAM_TX 0x0100 // this value indicates that host has 184 // data for DSP in DPRAM. 185 #define FT1000_ASIC_RESET_DSP 0x0400 // Responds to FT1000_ASIC_RESET_REQ 186 #define FT1000_DB_HB 0x1000 // Indicates that supervisor 187 // has a heartbeat message for DSP. 188 189 #define FT1000_DPRAM_BASE 0x0000 // Dual Port RAM starting offset 190 191 #define hi 0x6869 // PC Card heartbeat values 192 #define ho 0x686f // PC Card heartbeat values 193 194 // Magnemite specific defines 195 #define hi_mag 0x6968 // Byte swap hi to avoid additional system call 196 #define ho_mag 0x6f68 // Byte swap ho to avoid additional system call 197 198 // 199 // Bit field definitions for Host Interrupt Status Register 200 // 201 // Indicate the cause of an interrupt. 202 // 203 #define ISR_EMPTY 0x00 // no bits set 204 #define ISR_DOORBELL_ACK 0x01 // Doorbell acknowledge from DSP 205 #define ISR_DOORBELL_PEND 0x02 // Doorbell pending from DSP 206 #define ISR_RCV 0x04 // Packet available in Downlink FIFO 207 #define ISR_WATERMARK 0x08 // Watermark requirements satisfied 208 209 // Bit field definition for Host Interrupt Mask 210 #define ISR_MASK_NONE 0x0000 // no bits set 211 #define ISR_MASK_DOORBELL_ACK 0x0001 // Doorbell acknowledge mask 212 #define ISR_MASK_DOORBELL_PEND 0x0002 // Doorbell pending mask 213 #define ISR_MASK_RCV 0x0004 // Downlink Packet available mask 214 #define ISR_MASK_WATERMARK 0x0008 // Watermark interrupt mask 215 #define ISR_MASK_ALL 0xffff // Mask all interrupts 216 217 // Bit field definition for Host Control Register 218 #define DSP_RESET_BIT 0x0001 // Bit field to control dsp reset state 219 // (0 = out of reset 1 = reset) 220 #define ASIC_RESET_BIT 0x0002 // Bit field to control ASIC reset state 221 // (0 = out of reset 1 = reset) 222 223 // Default interrupt mask (Enable Doorbell pending and Packet available interrupts) 224 #define ISR_DEFAULT_MASK 0x7ff9 225 226 // Application specific IDs 227 #define DSPID 0x20 228 #define HOSTID 0x10 229 #define DSPAIRID 0x90 230 #define DRIVERID 0x00 231 #define NETWORKID 0x20 232 233 // Size of DPRAM Message 234 #define MAX_CMD_SQSIZE 1780 235 236 #define ENET_MAX_SIZE 1514 237 #define ENET_HEADER_SIZE 14 238 239 #define SLOWQ_TYPE 0 240 #define FASTQ_TYPE 1 241 242 #define MAX_DSP_SESS_REC 1024 243 244 #define DSP_QID_OFFSET 4 245 #define PSEUDOSZ 16 246 #define PSEUDOSZWRD 8 247 248 // Maximum number of occurrence of pseudo header errors before resetting PC Card. 249 #define MAX_PH_ERR 300 250 251 // Driver message types 252 #define MEDIA_STATE 0x0010 253 #define TIME_UPDATE 0x0020 254 #define DSP_PROVISION 0x0030 255 #define DSP_INIT_MSG 0x0050 256 #define DSP_HIBERNATE 0x0060 257 258 #define DSP_STORE_INFO 0x0070 259 #define DSP_GET_INFO 0x0071 260 #define GET_DRV_ERR_RPT_MSG 0x0073 261 #define RSP_DRV_ERR_RPT_MSG 0x0074 262 263 // Driver Error Messages for DSP 264 #define DSP_HB_INFO 0x7ef0 265 #define DSP_FIFO_INFO 0x7ef1 266 #define DSP_CONDRESET_INFO 0x7ef2 267 #define DSP_CMDLEN_INFO 0x7ef3 268 #define DSP_CMDPHCKSUM_INFO 0x7ef4 269 #define DSP_PKTPHCKSUM_INFO 0x7ef5 270 #define DSP_PKTLEN_INFO 0x7ef6 271 #define DSP_USER_RESET 0x7ef7 272 #define FIFO_FLUSH_MAXLIMIT 0x7ef8 273 #define FIFO_FLUSH_BADCNT 0x7ef9 274 #define FIFO_ZERO_LEN 0x7efa 275 276 #define HOST_QID_OFFSET 5 277 #define QTYPE_OFFSET 13 278 279 #define SUCCESS 0x00 280 #define FAILURE 0x01 281 #define TRUE 0x1 282 #define FALSE 0x0 283 284 #define MAX_NUM_APP 6 285 286 #define MAXIMUM_ASIC_HB_CNT 15 287 288 typedef struct _DRVMSG { 289 PSEUDO_HDR pseudo; 290 u16 type; 291 u16 length; 292 u8 data[0]; 293 } __attribute__ ((packed)) DRVMSG, *PDRVMSG; 294 295 typedef struct _MEDIAMSG { 296 PSEUDO_HDR pseudo; 297 u16 type; 298 u16 length; 299 u16 state; 300 u32 ip_addr; 301 u32 net_mask; 302 u32 gateway; 303 u32 dns_1; 304 u32 dns_2; 305 } __attribute__ ((packed)) MEDIAMSG, *PMEDIAMSG; 306 307 typedef struct _TIMEMSG { 308 PSEUDO_HDR pseudo; 309 u16 type; 310 u16 length; 311 u8 timeval[8]; 312 } __attribute__ ((packed)) TIMEMSG, *PTIMEMSG; 313 314 typedef struct _DSPINITMSG { 315 PSEUDO_HDR pseudo; 316 u16 type; 317 u16 length; 318 u8 DspVer[DSPVERSZ]; // DSP version number 319 u8 HwSerNum[HWSERNUMSZ]; // Hardware Serial Number 320 u8 Sku[SKUSZ]; // SKU 321 u8 eui64[EUISZ]; // EUI64 322 u8 ProductMode[MODESZ]; // Product Mode (Market/Production) 323 u8 RfCalVer[CALVERSZ]; // Rf Calibration version 324 u8 RfCalDate[CALDATESZ]; // Rf Calibration date 325 } __attribute__ ((packed)) DSPINITMSG, *PDSPINITMSG; 326 327 typedef struct _DSPHIBERNATE { 328 PSEUDO_HDR pseudo; 329 u16 type; 330 u16 length; 331 u32 timeout; 332 u16 sess_info[0]; 333 } DSPHIBERNATE, *PDSPHIBERNATE; 334 335 typedef struct _APP_INFO_BLOCK 336 { 337 u32 fileobject; // Application's file object 338 u16 app_id; // Application id 339 } APP_INFO_BLOCK, *PAPP_INFO_BLOCK; 340 341 typedef struct _PROV_RECORD { 342 struct list_head list; 343 u8 *pprov_data; 344 } PROV_RECORD, *PPROV_RECORD; 345 346 typedef struct _FT1000_INFO { 347 struct net_device_stats stats; 348 u16 DrvErrNum; 349 u16 AsicID; 350 int ASICResetNum; 351 int DspAsicReset; 352 int PktIntfErr; 353 int DSPResetNum; 354 int NumIOCTLBufs; 355 int IOCTLBufLvl; 356 int DeviceCreated; 357 int CardReady; 358 int DspHibernateFlag; 359 int DSPReady; 360 u8 DeviceName[15]; 361 int DeviceMajor; 362 int registered; 363 int mediastate; 364 u16 packetseqnum; 365 u8 squeseqnum; // sequence number on slow queue 366 spinlock_t dpram_lock; 367 u16 CurrentInterruptEnableMask; 368 int InterruptsEnabled; 369 u16 fifo_cnt; 370 u8 DspVer[DSPVERSZ]; // DSP version number 371 u8 HwSerNum[HWSERNUMSZ]; // Hardware Serial Number 372 u8 Sku[SKUSZ]; // SKU 373 u8 eui64[EUISZ]; // EUI64 374 time_t ConTm; // Connection Time 375 u16 LedStat; 376 u16 ConStat; 377 u16 ProgConStat; 378 u8 ProductMode[MODESZ]; 379 u8 RfCalVer[CALVERSZ]; 380 u8 RfCalDate[CALDATESZ]; 381 u16 DSP_TIME[4]; 382 struct list_head prov_list; 383 int appcnt; 384 APP_INFO_BLOCK app_info[MAX_NUM_APP]; 385 u16 DSPInfoBlklen; 386 u16 DrvMsgPend; 387 int (*ft1000_reset)(void *); 388 void *link; 389 u16 DSPInfoBlk[MAX_DSP_SESS_REC]; 390 union { 391 u16 Rec[MAX_DSP_SESS_REC]; 392 u32 MagRec[MAX_DSP_SESS_REC/2]; 393 } DSPSess; 394 struct proc_dir_entry *proc_ft1000; 395 char netdevname[IFNAMSIZ]; 396 } FT1000_INFO, *PFT1000_INFO; 397 398 typedef struct _DPRAM_BLK { 399 struct list_head list; 400 u16 *pbuffer; 401 } __attribute__ ((packed)) DPRAM_BLK, *PDPRAM_BLK; 402 403 extern u16 ft1000_read_dpram (struct net_device *dev, int offset); 404 extern void card_bootload(struct net_device *dev); 405 extern u16 ft1000_read_dpram_mag_16 (struct net_device *dev, int offset, int Index); 406 extern u32 ft1000_read_dpram_mag_32 (struct net_device *dev, int offset); 407 void ft1000_write_dpram_mag_32 (struct net_device *dev, int offset, u32 value); 408 409 #endif // _FT1000H_ 410