1 /* 2 * arch/arm/mach-footbridge/include/mach/hardware.h 3 * 4 * Copyright (C) 1998-1999 Russell King. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains the hardware definitions of the EBSA-285. 11 */ 12 #ifndef __ASM_ARCH_HARDWARE_H 13 #define __ASM_ARCH_HARDWARE_H 14 15 /* Virtual Physical Size 16 * 0xff800000 0x40000000 1MB X-Bus 17 * 0xff000000 0x7c000000 1MB PCI I/O space 18 * 0xfe000000 0x42000000 1MB CSR 19 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 20 * 0xfc000000 0x79000000 1MB PCI IACK/special space 21 * 0xfb000000 0x7a000000 16MB PCI Config type 1 22 * 0xfa000000 0x7b000000 16MB PCI Config type 0 23 * 0xf9000000 0x50000000 1MB Cache flush 24 * 0xf0000000 0x80000000 16MB ISA memory 25 */ 26 27 #ifdef CONFIG_MMU 28 #define MMU_IO(a, b) (a) 29 #else 30 #define MMU_IO(a, b) (b) 31 #endif 32 33 #define XBUS_SIZE 0x00100000 34 #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) 35 36 #define ARMCSR_SIZE 0x00100000 37 #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) 38 39 #define WFLUSH_SIZE 0x00100000 40 #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) 41 42 #define PCIIACK_SIZE 0x00100000 43 #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) 44 45 #define PCICFG1_SIZE 0x01000000 46 #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) 47 48 #define PCICFG0_SIZE 0x01000000 49 #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) 50 51 #define PCIMEM_SIZE 0x01000000 52 #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) 53 54 #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 55 #define XBUS_LED_AMBER (1 << 0) 56 #define XBUS_LED_GREEN (1 << 1) 57 #define XBUS_LED_RED (1 << 2) 58 #define XBUS_LED_TOGGLE (1 << 8) 59 60 #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 61 #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 62 #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 63 #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 64 #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 65 66 #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) 67 68 69 /* PIC irq control */ 70 #define PIC_LO 0x20 71 #define PIC_MASK_LO 0x21 72 #define PIC_HI 0xA0 73 #define PIC_MASK_HI 0xA1 74 75 /* GPIO pins */ 76 #define GPIO_CCLK 0x800 77 #define GPIO_DSCLK 0x400 78 #define GPIO_E2CLK 0x200 79 #define GPIO_IOLOAD 0x100 80 #define GPIO_RED_LED 0x080 81 #define GPIO_WDTIMER 0x040 82 #define GPIO_DATA 0x020 83 #define GPIO_IOCLK 0x010 84 #define GPIO_DONE 0x008 85 #define GPIO_FAN 0x004 86 #define GPIO_GREEN_LED 0x002 87 #define GPIO_RESET 0x001 88 89 /* CPLD pins */ 90 #define CPLD_DS_ENABLE 8 91 #define CPLD_7111_DISABLE 4 92 #define CPLD_UNMUTE 2 93 #define CPLD_FLASH_WR_ENABLE 1 94 95 #ifndef __ASSEMBLY__ 96 extern spinlock_t nw_gpio_lock; 97 extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 98 extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 99 extern unsigned int nw_gpio_read(void); 100 extern void nw_cpld_modify(unsigned int mask, unsigned int set); 101 #endif 102 103 #define pcibios_assign_all_busses() 1 104 105 #define PCIBIOS_MIN_IO 0x1000 106 #define PCIBIOS_MIN_MEM 0x81000000 107 108 #endif 109