1 /*
2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
17 #include <linux/io.h>
18
19 #include <asm/mach/irq.h>
20
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23
24 #include "irq-common.h"
25
26 /*
27 *****************************************
28 * TZIC Registers *
29 *****************************************
30 */
31
32 #define TZIC_INTCNTL 0x0000 /* Control register */
33 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
34 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
35 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
36 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
37 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
38 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
39 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
40 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
41 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
42 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
43 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
44 #define TZIC_PND0 0x0D00 /* Pending Register 0 */
45 #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
46 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
47 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
48 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
49
50 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
51
52 #ifdef CONFIG_FIQ
tzic_set_irq_fiq(unsigned int irq,unsigned int type)53 static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
54 {
55 unsigned int index, mask, value;
56
57 index = irq >> 5;
58 if (unlikely(index >= 4))
59 return -EINVAL;
60 mask = 1U << (irq & 0x1F);
61
62 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
63 if (type)
64 value &= ~mask;
65 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
66
67 return 0;
68 }
69 #endif
70
71 /**
72 * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
73 *
74 * @param d interrupt source
75 */
tzic_mask_irq(struct irq_data * d)76 static void tzic_mask_irq(struct irq_data *d)
77 {
78 int index, off;
79
80 index = d->irq >> 5;
81 off = d->irq & 0x1F;
82 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
83 }
84
85 /**
86 * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
87 *
88 * @param d interrupt source
89 */
tzic_unmask_irq(struct irq_data * d)90 static void tzic_unmask_irq(struct irq_data *d)
91 {
92 int index, off;
93
94 index = d->irq >> 5;
95 off = d->irq & 0x1F;
96 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
97 }
98
99 static unsigned int wakeup_intr[4];
100
101 /**
102 * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
103 *
104 * @param d interrupt source
105 * @param enable enable as wake-up if equal to non-zero
106 * disble as wake-up if equal to zero
107 *
108 * @return This function returns 0 on success.
109 */
tzic_set_wake_irq(struct irq_data * d,unsigned int enable)110 static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
111 {
112 unsigned int index, off;
113
114 index = d->irq >> 5;
115 off = d->irq & 0x1F;
116
117 if (index > 3)
118 return -EINVAL;
119
120 if (enable)
121 wakeup_intr[index] |= (1 << off);
122 else
123 wakeup_intr[index] &= ~(1 << off);
124
125 return 0;
126 }
127
128 static struct mxc_irq_chip mxc_tzic_chip = {
129 .base = {
130 .name = "MXC_TZIC",
131 .irq_ack = tzic_mask_irq,
132 .irq_mask = tzic_mask_irq,
133 .irq_unmask = tzic_unmask_irq,
134 .irq_set_wake = tzic_set_wake_irq,
135 },
136 #ifdef CONFIG_FIQ
137 .set_irq_fiq = tzic_set_irq_fiq,
138 #endif
139 };
140
141 /*
142 * This function initializes the TZIC hardware and disables all the
143 * interrupts. It registers the interrupt enable and disable functions
144 * to the kernel for each interrupt source.
145 */
tzic_init_irq(void __iomem * irqbase)146 void __init tzic_init_irq(void __iomem *irqbase)
147 {
148 int i;
149
150 tzic_base = irqbase;
151 /* put the TZIC into the reset value with
152 * all interrupts disabled
153 */
154 i = __raw_readl(tzic_base + TZIC_INTCNTL);
155
156 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
157 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
158 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
159
160 for (i = 0; i < 4; i++)
161 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
162
163 /* disable all interrupts */
164 for (i = 0; i < 4; i++)
165 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
166
167 /* all IRQ no FIQ Warning :: No selection */
168
169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
170 irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID);
173 }
174
175 #ifdef CONFIG_FIQ
176 /* Initialize FIQ */
177 init_FIQ();
178 #endif
179
180 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
181 }
182
183 /**
184 * tzic_enable_wake() - enable wakeup interrupt
185 *
186 * @param is_idle 1 if called in idle loop (ENSET0 register);
187 * 0 to be used when called from low power entry
188 * @return 0 if successful; non-zero otherwise
189 */
tzic_enable_wake(int is_idle)190 int tzic_enable_wake(int is_idle)
191 {
192 unsigned int i, v;
193
194 __raw_writel(1, tzic_base + TZIC_DSMINT);
195 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
196 return -EAGAIN;
197
198 for (i = 0; i < 4; i++) {
199 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
200 wakeup_intr[i];
201 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
202 }
203
204 return 0;
205 }
206