Searched refs:TRANSA_DPLL_ENABLE (Results 1 – 2 of 2) sorted by relevance
2770 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) in ironlake_pch_enable()2771 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); in ironlake_pch_enable()2931 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); in ironlake_crtc_disable()4944 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; in intel_crtc_mode_set()
2968 #define TRANSA_DPLL_ENABLE (1<<3) macro