Searched refs:Spare1 (Results 1 – 3 of 3) sorted by relevance
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; in chipcHw_ddrPhaseAlignInterruptEnable()1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; in chipcHw_ddrPhaseAlignInterruptDisable()1264 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; in chipcHw_vpmPhaseAlignInterruptMode()1266 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; in chipcHw_vpmPhaseAlignInterruptMode()
72 uint32_t Spare1; /* Phase align interrupts */ member
700 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()718 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()734 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()