Searched refs:SSB_PLLTYPE_1 (Results 1 – 4 of 4) sorted by relevance
110 *pll_type = SSB_PLLTYPE_1; in ssb_extif_get_clockcontrol()
1006 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()1042 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()1047 if ((plltype == SSB_PLLTYPE_1) || in ssb_calc_clock_rate()
427 if (plltype == SSB_PLLTYPE_1) { in ssb_chipco_serial_init()
40 #define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ macro