1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _bcmsrom_fmt_h_ 18 #define _bcmsrom_fmt_h_ 19 20 /* Maximum srom: 6 Kilobits == 768 bytes */ 21 #define SROM_MAX 768 22 #define SROM_MAXW 384 23 #define VARS_MAX 4096 24 25 /* PCI fields */ 26 #define PCI_F0DEVID 48 27 28 #define SROM_WORDS 64 29 30 #define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 31 32 #define SROM_SSID 2 33 34 #define SROM_WL1LHMAXP 29 35 36 #define SROM_WL1LPAB0 30 37 #define SROM_WL1LPAB1 31 38 #define SROM_WL1LPAB2 32 39 40 #define SROM_WL1HPAB0 33 41 #define SROM_WL1HPAB1 34 42 #define SROM_WL1HPAB2 35 43 44 #define SROM_MACHI_IL0 36 45 #define SROM_MACMID_IL0 37 46 #define SROM_MACLO_IL0 38 47 #define SROM_MACHI_ET0 39 48 #define SROM_MACMID_ET0 40 49 #define SROM_MACLO_ET0 41 50 #define SROM_MACHI_ET1 42 51 #define SROM_MACMID_ET1 43 52 #define SROM_MACLO_ET1 44 53 #define SROM3_MACHI 37 54 #define SROM3_MACMID 38 55 #define SROM3_MACLO 39 56 57 #define SROM_BXARSSI2G 40 58 #define SROM_BXARSSI5G 41 59 60 #define SROM_TRI52G 42 61 #define SROM_TRI5GHL 43 62 63 #define SROM_RXPO52G 45 64 65 #define SROM2_ENETPHY 45 66 67 #define SROM_AABREV 46 68 /* Fields in AABREV */ 69 #define SROM_BR_MASK 0x00ff 70 #define SROM_CC_MASK 0x0f00 71 #define SROM_CC_SHIFT 8 72 #define SROM_AA0_MASK 0x3000 73 #define SROM_AA0_SHIFT 12 74 #define SROM_AA1_MASK 0xc000 75 #define SROM_AA1_SHIFT 14 76 77 #define SROM_WL0PAB0 47 78 #define SROM_WL0PAB1 48 79 #define SROM_WL0PAB2 49 80 81 #define SROM_LEDBH10 50 82 #define SROM_LEDBH32 51 83 84 #define SROM_WL10MAXP 52 85 86 #define SROM_WL1PAB0 53 87 #define SROM_WL1PAB1 54 88 #define SROM_WL1PAB2 55 89 90 #define SROM_ITT 56 91 92 #define SROM_BFL 57 93 #define SROM_BFL2 28 94 #define SROM3_BFL2 61 95 96 #define SROM_AG10 58 97 98 #define SROM_CCODE 59 99 100 #define SROM_OPO 60 101 102 #define SROM3_LEDDC 62 103 104 #define SROM_CRCREV 63 105 106 /* SROM Rev 4: Reallocate the software part of the srom to accommodate 107 * MIMO features. It assumes up to two PCIE functions and 440 bytes 108 * of useable srom i.e. the useable storage in chips with OTP that 109 * implements hardware redundancy. 110 */ 111 112 #define SROM4_WORDS 220 113 114 #define SROM4_SIGN 32 115 #define SROM4_SIGNATURE 0x5372 116 117 #define SROM4_BREV 33 118 119 #define SROM4_BFL0 34 120 #define SROM4_BFL1 35 121 #define SROM4_BFL2 36 122 #define SROM4_BFL3 37 123 #define SROM5_BFL0 37 124 #define SROM5_BFL1 38 125 #define SROM5_BFL2 39 126 #define SROM5_BFL3 40 127 128 #define SROM4_MACHI 38 129 #define SROM4_MACMID 39 130 #define SROM4_MACLO 40 131 #define SROM5_MACHI 41 132 #define SROM5_MACMID 42 133 #define SROM5_MACLO 43 134 135 #define SROM4_CCODE 41 136 #define SROM4_REGREV 42 137 #define SROM5_CCODE 34 138 #define SROM5_REGREV 35 139 140 #define SROM4_LEDBH10 43 141 #define SROM4_LEDBH32 44 142 #define SROM5_LEDBH10 59 143 #define SROM5_LEDBH32 60 144 145 #define SROM4_LEDDC 45 146 #define SROM5_LEDDC 45 147 148 #define SROM4_AA 46 149 #define SROM4_AA2G_MASK 0x00ff 150 #define SROM4_AA2G_SHIFT 0 151 #define SROM4_AA5G_MASK 0xff00 152 #define SROM4_AA5G_SHIFT 8 153 154 #define SROM4_AG10 47 155 #define SROM4_AG32 48 156 157 #define SROM4_TXPID2G 49 158 #define SROM4_TXPID5G 51 159 #define SROM4_TXPID5GL 53 160 #define SROM4_TXPID5GH 55 161 162 #define SROM4_TXRXC 61 163 #define SROM4_TXCHAIN_MASK 0x000f 164 #define SROM4_TXCHAIN_SHIFT 0 165 #define SROM4_RXCHAIN_MASK 0x00f0 166 #define SROM4_RXCHAIN_SHIFT 4 167 #define SROM4_SWITCH_MASK 0xff00 168 #define SROM4_SWITCH_SHIFT 8 169 170 /* Per-path fields */ 171 #define MAX_PATH_SROM 4 172 #define SROM4_PATH0 64 173 #define SROM4_PATH1 87 174 #define SROM4_PATH2 110 175 #define SROM4_PATH3 133 176 177 #define SROM4_2G_ITT_MAXP 0 178 #define SROM4_2G_PA 1 179 #define SROM4_5G_ITT_MAXP 5 180 #define SROM4_5GLH_MAXP 6 181 #define SROM4_5G_PA 7 182 #define SROM4_5GL_PA 11 183 #define SROM4_5GH_PA 15 184 185 /* Fields in the ITT_MAXP and 5GLH_MAXP words */ 186 #define B2G_MAXP_MASK 0xff 187 #define B2G_ITT_SHIFT 8 188 #define B5G_MAXP_MASK 0xff 189 #define B5G_ITT_SHIFT 8 190 #define B5GH_MAXP_MASK 0xff 191 #define B5GL_MAXP_SHIFT 8 192 193 /* All the miriad power offsets */ 194 #define SROM4_2G_CCKPO 156 195 #define SROM4_2G_OFDMPO 157 196 #define SROM4_5G_OFDMPO 159 197 #define SROM4_5GL_OFDMPO 161 198 #define SROM4_5GH_OFDMPO 163 199 #define SROM4_2G_MCSPO 165 200 #define SROM4_5G_MCSPO 173 201 #define SROM4_5GL_MCSPO 181 202 #define SROM4_5GH_MCSPO 189 203 #define SROM4_CDDPO 197 204 #define SROM4_STBCPO 198 205 #define SROM4_BW40PO 199 206 #define SROM4_BWDUPPO 200 207 208 #define SROM4_CRCREV 219 209 210 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 211 * This is acombined srom for both MIMO and SISO boards, usable in 212 * the .130 4Kilobit OTP with hardware redundancy. 213 */ 214 215 #define SROM8_SIGN 64 216 217 #define SROM8_BREV 65 218 219 #define SROM8_BFL0 66 220 #define SROM8_BFL1 67 221 #define SROM8_BFL2 68 222 #define SROM8_BFL3 69 223 224 #define SROM8_MACHI 70 225 #define SROM8_MACMID 71 226 #define SROM8_MACLO 72 227 228 #define SROM8_CCODE 73 229 #define SROM8_REGREV 74 230 231 #define SROM8_LEDBH10 75 232 #define SROM8_LEDBH32 76 233 234 #define SROM8_LEDDC 77 235 236 #define SROM8_AA 78 237 238 #define SROM8_AG10 79 239 #define SROM8_AG32 80 240 241 #define SROM8_TXRXC 81 242 243 #define SROM8_BXARSSI2G 82 244 #define SROM8_BXARSSI5G 83 245 #define SROM8_TRI52G 84 246 #define SROM8_TRI5GHL 85 247 #define SROM8_RXPO52G 86 248 249 #define SROM8_FEM2G 87 250 #define SROM8_FEM5G 88 251 #define SROM8_FEM_ANTSWLUT_MASK 0xf800 252 #define SROM8_FEM_ANTSWLUT_SHIFT 11 253 #define SROM8_FEM_TR_ISO_MASK 0x0700 254 #define SROM8_FEM_TR_ISO_SHIFT 8 255 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8 256 #define SROM8_FEM_PDET_RANGE_SHIFT 3 257 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 258 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1 259 #define SROM8_FEM_TSSIPOS_MASK 0x0001 260 #define SROM8_FEM_TSSIPOS_SHIFT 0 261 262 #define SROM8_THERMAL 89 263 264 /* Temp sense related entries */ 265 #define SROM8_MPWR_RAWTS 90 266 #define SROM8_TS_SLP_OPT_CORRX 91 267 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 268 #define SROM8_FOC_HWIQ_IQSWP 92 269 270 /* Temperature delta for PHY calibration */ 271 #define SROM8_PHYCAL_TEMPDELTA 93 272 273 /* Per-path offsets & fields */ 274 #define SROM8_PATH0 96 275 #define SROM8_PATH1 112 276 #define SROM8_PATH2 128 277 #define SROM8_PATH3 144 278 279 #define SROM8_2G_ITT_MAXP 0 280 #define SROM8_2G_PA 1 281 #define SROM8_5G_ITT_MAXP 4 282 #define SROM8_5GLH_MAXP 5 283 #define SROM8_5G_PA 6 284 #define SROM8_5GL_PA 9 285 #define SROM8_5GH_PA 12 286 287 /* All the miriad power offsets */ 288 #define SROM8_2G_CCKPO 160 289 290 #define SROM8_2G_OFDMPO 161 291 #define SROM8_5G_OFDMPO 163 292 #define SROM8_5GL_OFDMPO 165 293 #define SROM8_5GH_OFDMPO 167 294 295 #define SROM8_2G_MCSPO 169 296 #define SROM8_5G_MCSPO 177 297 #define SROM8_5GL_MCSPO 185 298 #define SROM8_5GH_MCSPO 193 299 300 #define SROM8_CDDPO 201 301 #define SROM8_STBCPO 202 302 #define SROM8_BW40PO 203 303 #define SROM8_BWDUPPO 204 304 305 /* SISO PA parameters are in the path0 spaces */ 306 #define SROM8_SISO 96 307 308 /* Legacy names for SISO PA paramters */ 309 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 310 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 311 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 312 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 313 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 314 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 315 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 316 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 317 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 318 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 319 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 320 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 321 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 322 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 323 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 324 325 #define SROM8_CRCREV 219 326 327 /* SROM REV 9 */ 328 #define SROM9_2GPO_CCKBW20 160 329 #define SROM9_2GPO_CCKBW20UL 161 330 #define SROM9_2GPO_LOFDMBW20 162 331 #define SROM9_2GPO_LOFDMBW20UL 164 332 333 #define SROM9_5GLPO_LOFDMBW20 166 334 #define SROM9_5GLPO_LOFDMBW20UL 168 335 #define SROM9_5GMPO_LOFDMBW20 170 336 #define SROM9_5GMPO_LOFDMBW20UL 172 337 #define SROM9_5GHPO_LOFDMBW20 174 338 #define SROM9_5GHPO_LOFDMBW20UL 176 339 340 #define SROM9_2GPO_MCSBW20 178 341 #define SROM9_2GPO_MCSBW20UL 180 342 #define SROM9_2GPO_MCSBW40 182 343 344 #define SROM9_5GLPO_MCSBW20 184 345 #define SROM9_5GLPO_MCSBW20UL 186 346 #define SROM9_5GLPO_MCSBW40 188 347 #define SROM9_5GMPO_MCSBW20 190 348 #define SROM9_5GMPO_MCSBW20UL 192 349 #define SROM9_5GMPO_MCSBW40 194 350 #define SROM9_5GHPO_MCSBW20 196 351 #define SROM9_5GHPO_MCSBW20UL 198 352 #define SROM9_5GHPO_MCSBW40 200 353 354 #define SROM9_PO_MCS32 202 355 #define SROM9_PO_LOFDM40DUP 203 356 357 #define SROM9_REV_CRC 219 358 359 typedef struct { 360 u8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 361 u8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 362 u8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 363 u8 triso; /* TR switch isolation */ 364 u8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 365 } srom_fem_t; 366 367 #endif /* _bcmsrom_fmt_h_ */ 368