1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SDIO_H 18 #define _SDIO_H 19 20 #ifdef BCMSDIO 21 22 /* CCCR structure for function 0 */ 23 typedef volatile struct { 24 u8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 25 u8 sd_rev; /* RO, sd spec revision */ 26 u8 io_en; /* I/O enable */ 27 u8 io_rdy; /* I/O ready reg */ 28 u8 intr_ctl; /* Master and per function interrupt enable control */ 29 u8 intr_status; /* RO, interrupt pending status */ 30 u8 io_abort; /* read/write abort or reset all functions */ 31 u8 bus_inter; /* bus interface control */ 32 u8 capability; /* RO, card capability */ 33 34 u8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 35 u8 cis_base_mid; 36 u8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 37 38 /* suspend/resume registers */ 39 u8 bus_suspend; /* 0xC */ 40 u8 func_select; /* 0xD */ 41 u8 exec_flag; /* 0xE */ 42 u8 ready_flag; /* 0xF */ 43 44 u8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 45 46 u8 power_control; /* 0x12 (SDIO version 1.10) */ 47 48 u8 speed_control; /* 0x13 */ 49 } sdio_regs_t; 50 51 /* SDIO Device CCCR offsets */ 52 #define SDIOD_CCCR_REV 0x00 53 #define SDIOD_CCCR_SDREV 0x01 54 #define SDIOD_CCCR_IOEN 0x02 55 #define SDIOD_CCCR_IORDY 0x03 56 #define SDIOD_CCCR_INTEN 0x04 57 #define SDIOD_CCCR_INTPEND 0x05 58 #define SDIOD_CCCR_IOABORT 0x06 59 #define SDIOD_CCCR_BICTRL 0x07 60 #define SDIOD_CCCR_CAPABLITIES 0x08 61 #define SDIOD_CCCR_CISPTR_0 0x09 62 #define SDIOD_CCCR_CISPTR_1 0x0A 63 #define SDIOD_CCCR_CISPTR_2 0x0B 64 #define SDIOD_CCCR_BUSSUSP 0x0C 65 #define SDIOD_CCCR_FUNCSEL 0x0D 66 #define SDIOD_CCCR_EXECFLAGS 0x0E 67 #define SDIOD_CCCR_RDYFLAGS 0x0F 68 #define SDIOD_CCCR_BLKSIZE_0 0x10 69 #define SDIOD_CCCR_BLKSIZE_1 0x11 70 #define SDIOD_CCCR_POWER_CONTROL 0x12 71 #define SDIOD_CCCR_SPEED_CONTROL 0x13 72 73 /* Broadcom extensions (corerev >= 1) */ 74 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 75 76 /* cccr_sdio_rev */ 77 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 78 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 79 80 /* sd_rev */ 81 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 82 83 /* io_en */ 84 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 85 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 86 87 /* io_rdys */ 88 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 89 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 90 91 /* intr_ctl */ 92 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 93 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 94 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 95 96 /* intr_status */ 97 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 98 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 99 100 /* io_abort */ 101 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 102 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 103 104 /* bus_inter */ 105 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 106 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 107 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 108 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 109 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 110 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 111 112 /* capability */ 113 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 114 #define SDIO_CAP_LSC 0x40 /* low speed card */ 115 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ 116 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ 117 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 118 #define SDIO_CAP_SRW 0x04 /* support read wait */ 119 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 120 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ 121 122 /* power_control */ 123 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 124 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ 125 126 /* speed_control (control device entry into high-speed clocking mode) */ 127 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 128 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 129 130 /* brcm sepint */ 131 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 132 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 133 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ 134 135 /* FBR structure for function 1-7, FBR addresses and register offsets */ 136 typedef volatile struct { 137 u8 devctr; /* device interface, CSA control */ 138 u8 ext_dev; /* extended standard I/O device type code */ 139 u8 pwr_sel; /* power selection support */ 140 u8 PAD[6]; /* reserved */ 141 142 u8 cis_low; /* CIS LSB */ 143 u8 cis_mid; 144 u8 cis_high; /* CIS MSB */ 145 u8 csa_low; /* code storage area, LSB */ 146 u8 csa_mid; 147 u8 csa_high; /* code storage area, MSB */ 148 u8 csa_dat_win; /* data access window to function */ 149 150 u8 fnx_blk_size[2]; /* block size, little endian */ 151 } sdio_fbr_t; 152 153 /* Maximum number of I/O funcs */ 154 #define SDIOD_MAX_IOFUNCS 7 155 156 /* SDIO Device FBR Start Address */ 157 #define SDIOD_FBR_STARTADDR 0x100 158 159 /* SDIO Device FBR Size */ 160 #define SDIOD_FBR_SIZE 0x100 161 162 /* Macro to calculate FBR register base */ 163 #define SDIOD_FBR_BASE(n) ((n) * 0x100) 164 165 /* Function register offsets */ 166 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 167 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 168 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 169 170 /* SDIO Function CIS ptr offset */ 171 #define SDIOD_FBR_CISPTR_0 0x09 172 #define SDIOD_FBR_CISPTR_1 0x0A 173 #define SDIOD_FBR_CISPTR_2 0x0B 174 175 /* Code Storage Area pointer */ 176 #define SDIOD_FBR_CSA_ADDR_0 0x0C 177 #define SDIOD_FBR_CSA_ADDR_1 0x0D 178 #define SDIOD_FBR_CSA_ADDR_2 0x0E 179 #define SDIOD_FBR_CSA_DATA 0x0F 180 181 /* SDIO Function I/O Block Size */ 182 #define SDIOD_FBR_BLKSIZE_0 0x10 183 #define SDIOD_FBR_BLKSIZE_1 0x11 184 185 /* devctr */ 186 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 187 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 188 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 189 /* interface codes */ 190 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 191 #define SDIOD_DIC_UART 1 192 #define SDIOD_DIC_BLUETOOTH_A 2 193 #define SDIOD_DIC_BLUETOOTH_B 3 194 #define SDIOD_DIC_GPS 4 195 #define SDIOD_DIC_CAMERA 5 196 #define SDIOD_DIC_PHS 6 197 #define SDIOD_DIC_WLAN 7 198 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ 199 200 /* pwr_sel */ 201 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 202 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 203 204 /* misc defines */ 205 #define SDIO_FUNC_0 0 206 #define SDIO_FUNC_1 1 207 #define SDIO_FUNC_2 2 208 #define SDIO_FUNC_3 3 209 #define SDIO_FUNC_4 4 210 #define SDIO_FUNC_5 5 211 #define SDIO_FUNC_6 6 212 #define SDIO_FUNC_7 7 213 214 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 215 #define SD_CARD_TYPE_IO 1 /* IO only card */ 216 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 217 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 218 219 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ 220 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ 221 222 /* Card registers: status bit position */ 223 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 224 #define CARDREG_STATUS_BIT_COMCRCERROR 23 225 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 226 #define CARDREG_STATUS_BIT_ERROR 19 227 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 228 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 229 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 230 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 231 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 232 233 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 234 #define SD_CMD_SEND_OPCOND 1 235 #define SD_CMD_MMC_SET_RCA 3 236 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 237 #define SD_CMD_SELECT_DESELECT_CARD 7 238 #define SD_CMD_SEND_CSD 9 239 #define SD_CMD_SEND_CID 10 240 #define SD_CMD_STOP_TRANSMISSION 12 241 #define SD_CMD_SEND_STATUS 13 242 #define SD_CMD_GO_INACTIVE_STATE 15 243 #define SD_CMD_SET_BLOCKLEN 16 244 #define SD_CMD_READ_SINGLE_BLOCK 17 245 #define SD_CMD_READ_MULTIPLE_BLOCK 18 246 #define SD_CMD_WRITE_BLOCK 24 247 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 248 #define SD_CMD_PROGRAM_CSD 27 249 #define SD_CMD_SET_WRITE_PROT 28 250 #define SD_CMD_CLR_WRITE_PROT 29 251 #define SD_CMD_SEND_WRITE_PROT 30 252 #define SD_CMD_ERASE_WR_BLK_START 32 253 #define SD_CMD_ERASE_WR_BLK_END 33 254 #define SD_CMD_ERASE 38 255 #define SD_CMD_LOCK_UNLOCK 42 256 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 257 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 258 #define SD_CMD_APP_CMD 55 259 #define SD_CMD_GEN_CMD 56 260 #define SD_CMD_READ_OCR 58 261 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 262 #define SD_ACMD_SD_STATUS 13 263 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 264 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 265 #define SD_ACMD_SD_SEND_OP_COND 41 266 #define SD_ACMD_SET_CLR_CARD_DETECT 42 267 #define SD_ACMD_SEND_SCR 51 268 269 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 270 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 271 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 272 #define SD_IO_RW_NORMAL 0 /* no RAW */ 273 #define SD_IO_RW_RAW 1 /* RAW */ 274 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 275 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 276 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 277 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 278 279 /* build SD_CMD_IO_RW_DIRECT Argument */ 280 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 281 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ 282 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) 283 284 /* build SD_CMD_IO_RW_EXTENDED Argument */ 285 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 286 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ 287 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) 288 289 /* SDIO response parameters */ 290 #define SD_RSP_NO_NONE 0 291 #define SD_RSP_NO_1 1 292 #define SD_RSP_NO_2 2 293 #define SD_RSP_NO_3 3 294 #define SD_RSP_NO_4 4 295 #define SD_RSP_NO_5 5 296 #define SD_RSP_NO_6 6 297 298 /* Modified R6 response (to CMD3) */ 299 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 300 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 301 #define SD_RSP_MR6_ERROR 0x2000 302 303 /* Modified R1 in R4 Response (to CMD5) */ 304 #define SD_RSP_MR1_SBIT 0x80 305 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 306 #define SD_RSP_MR1_RFU5 0x20 307 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 308 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 309 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 310 #define SD_RSP_MR1_RFU1 0x02 311 #define SD_RSP_MR1_IDLE_STATE 0x01 312 313 /* R5 response (to CMD52 and CMD53) */ 314 #define SD_RSP_R5_COM_CRC_ERROR 0x80 315 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 316 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 317 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 318 #define SD_RSP_R5_ERROR 0x08 319 #define SD_RSP_R5_RFU 0x04 320 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 321 #define SD_RSP_R5_OUT_OF_RANGE 0x01 322 323 #define SD_RSP_R5_ERRBITS 0xCB 324 325 /* ------------------------------------------------ 326 * SDIO Commands and responses 327 * 328 * I/O only commands are: 329 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 330 * ------------------------------------------------ 331 */ 332 333 /* SDIO Commands */ 334 #define SDIOH_CMD_0 0 335 #define SDIOH_CMD_3 3 336 #define SDIOH_CMD_5 5 337 #define SDIOH_CMD_7 7 338 #define SDIOH_CMD_15 15 339 #define SDIOH_CMD_52 52 340 #define SDIOH_CMD_53 53 341 #define SDIOH_CMD_59 59 342 343 /* SDIO Command Responses */ 344 #define SDIOH_RSP_NONE 0 345 #define SDIOH_RSP_R1 1 346 #define SDIOH_RSP_R2 2 347 #define SDIOH_RSP_R3 3 348 #define SDIOH_RSP_R4 4 349 #define SDIOH_RSP_R5 5 350 #define SDIOH_RSP_R6 6 351 352 /* 353 * SDIO Response Error flags 354 */ 355 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 356 357 /* ------------------------------------------------ 358 * SDIO Command structures. I/O only commands are: 359 * 360 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 361 * ------------------------------------------------ 362 */ 363 364 #define CMD5_OCR_M BITFIELD_MASK(24) 365 #define CMD5_OCR_S 0 366 367 #define CMD7_RCA_M BITFIELD_MASK(16) 368 #define CMD7_RCA_S 16 369 370 #define CMD_15_RCA_M BITFIELD_MASK(16) 371 #define CMD_15_RCA_S 16 372 373 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 374 */ 375 #define CMD52_DATA_S 0 376 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 377 #define CMD52_REG_ADDR_S 9 378 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ 379 #define CMD52_RAW_S 27 380 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 381 #define CMD52_FUNCTION_S 28 382 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 383 #define CMD52_RW_FLAG_S 31 384 385 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 386 #define CMD53_BYTE_BLK_CNT_S 0 387 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 388 #define CMD53_REG_ADDR_S 9 389 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 390 #define CMD53_OP_CODE_S 26 391 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 392 #define CMD53_BLK_MODE_S 27 393 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 394 #define CMD53_FUNCTION_S 28 395 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 396 #define CMD53_RW_FLAG_S 31 397 398 /* ------------------------------------------------------ 399 * SDIO Command Response structures for SD1 and SD4 modes 400 * ----------------------------------------------------- 401 */ 402 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 403 #define RSP4_IO_OCR_S 0 404 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 405 #define RSP4_STUFF_S 24 406 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ 407 #define RSP4_MEM_PRESENT_S 27 408 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 409 #define RSP4_NUM_FUNCS_S 28 410 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ 411 #define RSP4_CARD_READY_S 31 412 413 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] 414 */ 415 #define RSP6_STATUS_S 0 416 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 417 #define RSP6_IO_RCA_S 16 418 419 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 420 #define RSP1_AKE_SEQ_ERROR_S 3 421 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 422 #define RSP1_APP_CMD_S 5 423 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 424 #define RSP1_READY_FOR_DATA_S 8 425 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card 426 * when Cmd was received 427 */ 428 #define RSP1_CURR_STATE_S 9 429 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 430 #define RSP1_EARSE_RESET_S 13 431 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 432 #define RSP1_CARD_ECC_DISABLE_S 14 433 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 434 #define RSP1_WP_ERASE_SKIP_S 15 435 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits 436 * of CSD 437 */ 438 #define RSP1_CID_CSD_OVERW_S 16 439 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 440 #define RSP1_ERROR_S 19 441 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 442 #define RSP1_CC_ERROR_S 20 443 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed 444 * to correct data 445 */ 446 #define RSP1_CARD_ECC_FAILED_S 21 447 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 448 #define RSP1_ILLEGAL_CMD_S 22 449 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed 450 */ 451 #define RSP1_COM_CRC_ERROR_S 23 452 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 453 #define RSP1_LOCK_UNLOCK_FAIL_S 24 454 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 455 #define RSP1_CARD_LOCKED_S 25 456 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program 457 * write-protected blocks 458 */ 459 #define RSP1_WP_VIOLATION_S 26 460 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 461 #define RSP1_ERASE_PARAM_S 27 462 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 463 #define RSP1_ERASE_SEQ_ERR_S 28 464 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ 465 #define RSP1_BLK_LEN_ERR_S 29 466 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 467 #define RSP1_ADDR_ERR_S 30 468 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 469 #define RSP1_OUT_OF_RANGE_S 31 470 471 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 472 #define RSP5_DATA_S 0 473 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 474 #define RSP5_FLAGS_S 8 475 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 476 #define RSP5_STUFF_S 16 477 478 /* ---------------------------------------------- 479 * SDIO Command Response structures for SPI mode 480 * ---------------------------------------------- 481 */ 482 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 483 #define SPIRSP4_IO_OCR_S 0 484 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 485 #define SPIRSP4_STUFF_S 16 486 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ 487 #define SPIRSP4_MEM_PRESENT_S 19 488 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 489 #define SPIRSP4_NUM_FUNCS_S 20 490 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 491 #define SPIRSP4_CARD_READY_S 23 492 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ 493 #define SPIRSP4_IDLE_STATE_S 24 494 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 495 #define SPIRSP4_ILLEGAL_CMD_S 26 496 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 497 #define SPIRSP4_COM_CRC_ERROR_S 27 498 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 499 */ 500 #define SPIRSP4_FUNC_NUM_ERROR_S 28 501 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 502 #define SPIRSP4_PARAM_ERROR_S 30 503 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 504 #define SPIRSP4_START_BIT_S 31 505 506 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 507 #define SPIRSP5_DATA_S 16 508 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ 509 #define SPIRSP5_IDLE_STATE_S 24 510 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 511 #define SPIRSP5_ILLEGAL_CMD_S 26 512 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 513 #define SPIRSP5_COM_CRC_ERROR_S 27 514 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 515 */ 516 #define SPIRSP5_FUNC_NUM_ERROR_S 28 517 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 518 #define SPIRSP5_PARAM_ERROR_S 30 519 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 520 #define SPIRSP5_START_BIT_S 31 521 522 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 523 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error 524 */ 525 #define RSP6STAT_AKE_SEQ_ERROR_S 3 526 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 527 #define RSP6STAT_APP_CMD_S 5 528 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data 529 * (buff empty) 530 */ 531 #define RSP6STAT_READY_FOR_DATA_S 8 532 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at 533 * Cmd reception 534 */ 535 #define RSP6STAT_CURR_STATE_S 9 536 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 537 */ 538 #define RSP6STAT_ERROR_S 13 539 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for 540 * card state Bit 22 541 */ 542 #define RSP6STAT_ILLEGAL_CMD_S 14 543 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command 544 * failed Bit 23 545 */ 546 #define RSP6STAT_COM_CRC_ERROR_S 15 547 548 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 549 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 550 551 #endif /* def BCMSDIO */ 552 #endif /* _SDIO_H */ 553