1 /* 2 * Blackfin Secure Digital Host (SDH) definitions 3 * 4 * Copyright 2008-2010 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #ifndef __BFIN_SDH_H__ 10 #define __BFIN_SDH_H__ 11 12 /* Platform resources */ 13 struct bfin_sd_host { 14 int dma_chan; 15 int irq_int0; 16 int irq_int1; 17 u16 pin_req[7]; 18 }; 19 20 /* SDH_COMMAND bitmasks */ 21 #define CMD_IDX 0x3f /* Command Index */ 22 #define CMD_RSP (1 << 6) /* Response */ 23 #define CMD_L_RSP (1 << 7) /* Long Response */ 24 #define CMD_INT_E (1 << 8) /* Command Interrupt */ 25 #define CMD_PEND_E (1 << 9) /* Command Pending */ 26 #define CMD_E (1 << 10) /* Command Enable */ 27 28 /* SDH_PWR_CTL bitmasks */ 29 #define PWR_ON 0x3 /* Power On */ 30 #define SD_CMD_OD (1 << 6) /* Open Drain Output */ 31 #define ROD_CTL (1 << 7) /* Rod Control */ 32 33 /* SDH_CLK_CTL bitmasks */ 34 #define CLKDIV 0xff /* MC_CLK Divisor */ 35 #define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ 36 #define PWR_SV_E (1 << 9) /* Power Save Enable */ 37 #define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ 38 #define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ 39 40 /* SDH_RESP_CMD bitmasks */ 41 #define RESP_CMD 0x3f /* Response Command */ 42 43 /* SDH_DATA_CTL bitmasks */ 44 #define DTX_E (1 << 0) /* Data Transfer Enable */ 45 #define DTX_DIR (1 << 1) /* Data Transfer Direction */ 46 #define DTX_MODE (1 << 2) /* Data Transfer Mode */ 47 #define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ 48 #define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ 49 50 /* SDH_STATUS bitmasks */ 51 #define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ 52 #define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */ 53 #define CMD_TIME_OUT (1 << 2) /* CMD Time Out */ 54 #define DAT_TIME_OUT (1 << 3) /* Data Time Out */ 55 #define TX_UNDERRUN (1 << 4) /* Transmit Underrun */ 56 #define RX_OVERRUN (1 << 5) /* Receive Overrun */ 57 #define CMD_RESP_END (1 << 6) /* CMD Response End */ 58 #define CMD_SENT (1 << 7) /* CMD Sent */ 59 #define DAT_END (1 << 8) /* Data End */ 60 #define START_BIT_ERR (1 << 9) /* Start Bit Error */ 61 #define DAT_BLK_END (1 << 10) /* Data Block End */ 62 #define CMD_ACT (1 << 11) /* CMD Active */ 63 #define TX_ACT (1 << 12) /* Transmit Active */ 64 #define RX_ACT (1 << 13) /* Receive Active */ 65 #define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */ 66 #define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */ 67 #define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */ 68 #define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ 69 #define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */ 70 #define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ 71 #define TX_DAT_RDY (1 << 20) /* Transmit Data Available */ 72 #define RX_FIFO_RDY (1 << 21) /* Receive Data Available */ 73 74 /* SDH_STATUS_CLR bitmasks */ 75 #define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */ 76 #define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */ 77 #define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */ 78 #define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */ 79 #define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */ 80 #define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ 81 #define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */ 82 #define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */ 83 #define DAT_END_STAT (1 << 8) /* Data End Status */ 84 #define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */ 85 #define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */ 86 87 /* SDH_MASK0 bitmasks */ 88 #define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */ 89 #define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */ 90 #define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */ 91 #define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */ 92 #define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ 93 #define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ 94 #define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ 95 #define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ 96 #define DAT_END_MASK (1 << 8) /* Data End Mask */ 97 #define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */ 98 #define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ 99 #define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ 100 #define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ 101 #define RX_ACT_MASK (1 << 13) /* Receive Active Mask */ 102 #define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */ 103 #define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */ 104 #define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */ 105 #define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ 106 #define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */ 107 #define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ 108 #define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */ 109 #define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ 110 111 /* SDH_FIFO_CNT bitmasks */ 112 #define FIFO_COUNT 0x7fff /* FIFO Count */ 113 114 /* SDH_E_STATUS bitmasks */ 115 #define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ 116 #define SD_CARD_DET (1 << 4) /* SD Card Detect */ 117 118 /* SDH_E_MASK bitmasks */ 119 #define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ 120 #define SCD_MSK (1 << 6) /* Mask Card Detect */ 121 122 /* SDH_CFG bitmasks */ 123 #define CLKS_EN (1 << 0) /* Clocks Enable */ 124 #define SD4E (1 << 2) /* SDIO 4-Bit Enable */ 125 #define MWE (1 << 3) /* Moving Window Enable */ 126 #define SD_RST (1 << 4) /* SDMMC Reset */ 127 #define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ 128 #define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ 129 #define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ 130 131 /* SDH_RD_WAIT_EN bitmasks */ 132 #define RWR (1 << 0) /* Read Wait Request */ 133 134 #endif 135