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Searched refs:S6_REG_GREG1 (Results 1 – 4 of 4) sorted by relevance

/linux-2.6.39/arch/xtensa/platforms/s6105/
Dsetup.c38 reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL); in platform_setup()
43 writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL); in platform_setup()
45 reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE); in platform_setup()
48 writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE); in platform_setup()
50 reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA); in platform_setup()
53 writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA); in platform_setup()
/linux-2.6.39/arch/xtensa/variants/s6000/
Ddelay.c12 u32 tstamp = S6_REG_GREG1 + S6_GREG1_GLOBAL_TIMER; in platform_calibrate_ccount()
/linux-2.6.39/arch/xtensa/variants/s6000/include/variant/
Dhardware.h30 #define S6_REG_GREG1 (S6_REG_SCB + 0x70000) macro
/linux-2.6.39/drivers/net/
Ds6gmac.c706 u32 pllsel = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL); in s6gmac_set_rgmii_txclock()
721 writel(pllsel, S6_REG_GREG1 + S6_GREG1_PLLSEL); in s6gmac_set_rgmii_txclock()