1 /* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * EXYNOS4 - Power management unit definition 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_REGS_PMU_H 14 #define __ASM_ARCH_REGS_PMU_H __FILE__ 15 16 #include <mach/map.h> 17 18 #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 19 20 #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) 21 22 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) 23 24 #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) 25 26 #define S5P_USE_STANDBY_WFI0 (1 << 16) 27 #define S5P_USE_STANDBY_WFI1 (1 << 17) 28 #define S5P_USE_STANDBY_WFE0 (1 << 24) 29 #define S5P_USE_STANDBY_WFE1 (1 << 25) 30 #define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) 31 32 #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 33 #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 34 #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) 35 36 #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) 37 #define S5P_MIPI_DPHY_ENABLE (1 << 0) 38 #define S5P_MIPI_DPHY_SRESETN (1 << 1) 39 #define S5P_MIPI_DPHY_MRESETN (1 << 2) 40 41 #define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) 42 #define S5P_INFORM0 S5P_PMUREG(0x0800) 43 #define S5P_INFORM1 S5P_PMUREG(0x0804) 44 #define S5P_INFORM2 S5P_PMUREG(0x0808) 45 #define S5P_INFORM3 S5P_PMUREG(0x080C) 46 #define S5P_INFORM4 S5P_PMUREG(0x0810) 47 #define S5P_INFORM5 S5P_PMUREG(0x0814) 48 #define S5P_INFORM6 S5P_PMUREG(0x0818) 49 #define S5P_INFORM7 S5P_PMUREG(0x081C) 50 51 #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) 52 #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) 53 #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) 54 #define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) 55 #define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) 56 #define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) 57 #define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) 58 #define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) 59 #define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) 60 #define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) 61 #define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) 62 #define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) 63 #define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) 64 #define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) 65 #define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) 66 #define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) 67 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) 68 #define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) 69 #define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) 70 #define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) 71 #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) 72 #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) 73 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) 74 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) 75 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) 76 #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) 77 #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) 78 #define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) 79 #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) 80 #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) 81 #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) 82 #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) 83 #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) 84 #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) 85 #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) 86 #define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) 87 #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) 88 #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) 89 #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) 90 #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) 91 #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) 92 #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) 93 #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) 94 #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) 95 #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) 96 #define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) 97 #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) 98 #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) 99 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) 100 #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) 101 #define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) 102 #define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) 103 #define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) 104 #define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) 105 #define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) 106 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) 107 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) 108 #define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) 109 #define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) 110 #define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) 111 #define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) 112 #define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) 113 #define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) 114 #define S5P_TV_LOWPWR S5P_PMUREG(0x1384) 115 #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) 116 #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) 117 #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) 118 #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) 119 #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) 120 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) 121 #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) 122 123 #define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) 124 #define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) 125 #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) 126 #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) 127 #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) 128 129 #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) 130 #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) 131 #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) 132 #define S5P_TV_OPTION S5P_PMUREG(0x3C28) 133 #define S5P_MFC_OPTION S5P_PMUREG(0x3C48) 134 #define S5P_G3D_OPTION S5P_PMUREG(0x3C68) 135 #define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) 136 #define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) 137 #define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) 138 #define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) 139 #define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) 140 141 #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) 142 #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) 143 #define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) 144 #define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) 145 #define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) 146 #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) 147 #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) 148 149 #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) 150 #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) 151 #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 152 #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) 153 #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) 154 #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) 155 #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 156 157 #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 158 #define S5P_INT_LOCAL_PWR_EN 0x7 159 160 #define S5P_CHECK_SLEEP 0x00000BAD 161 162 #endif /* __ASM_ARCH_REGS_PMU_H */ 163