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Searched refs:S5P_CLK_DIV0 (Results 1 – 8 of 8) sorted by relevance

/linux-2.6.39/arch/arm/mach-s5p6442/
Dclock.c214 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
223 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
232 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
241 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
250 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
259 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
/linux-2.6.39/arch/arm/mach-s5pv210/
Dclock.c80 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
146 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
1167 clkdiv0 = __raw_readl(S5P_CLK_DIV0); in s5pv210_setup_clocks()
Dcpufreq.c250 reg = __raw_readl(S5P_CLK_DIV0); in s5pv210_target()
266 __raw_writel(reg, S5P_CLK_DIV0); in s5pv210_target()
Dpm.c43 SAVE_ITEM(S5P_CLK_DIV0),
/linux-2.6.39/arch/arm/mach-s5pc100/include/mach/
Dregs-clock.h37 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
/linux-2.6.39/arch/arm/mach-s5p6442/include/mach/
Dregs-clock.h41 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
/linux-2.6.39/arch/arm/mach-s5pc100/
Dclock.c127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
/linux-2.6.39/arch/arm/mach-s5pv210/include/mach/
Dregs-clock.h42 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro