1 /* arch/arm/mach-s3c2410/include/mach/regs-iis.h 2 * 3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * S3C2410 IIS register definition 11 */ 12 13 #ifndef __ASM_ARCH_REGS_IIS_H 14 #define __ASM_ARCH_REGS_IIS_H 15 16 #define S3C2410_IISCON (0x00) 17 18 #define S3C2410_IISCON_LRINDEX (1<<8) 19 #define S3C2410_IISCON_TXFIFORDY (1<<7) 20 #define S3C2410_IISCON_RXFIFORDY (1<<6) 21 #define S3C2410_IISCON_TXDMAEN (1<<5) 22 #define S3C2410_IISCON_RXDMAEN (1<<4) 23 #define S3C2410_IISCON_TXIDLE (1<<3) 24 #define S3C2410_IISCON_RXIDLE (1<<2) 25 #define S3C2410_IISCON_PSCEN (1<<1) 26 #define S3C2410_IISCON_IISEN (1<<0) 27 28 #define S3C2410_IISMOD (0x04) 29 30 #define S3C2440_IISMOD_MPLL (1<<9) 31 #define S3C2410_IISMOD_SLAVE (1<<8) 32 #define S3C2410_IISMOD_NOXFER (0<<6) 33 #define S3C2410_IISMOD_RXMODE (1<<6) 34 #define S3C2410_IISMOD_TXMODE (2<<6) 35 #define S3C2410_IISMOD_TXRXMODE (3<<6) 36 #define S3C2410_IISMOD_LR_LLOW (0<<5) 37 #define S3C2410_IISMOD_LR_RLOW (1<<5) 38 #define S3C2410_IISMOD_IIS (0<<4) 39 #define S3C2410_IISMOD_MSB (1<<4) 40 #define S3C2410_IISMOD_8BIT (0<<3) 41 #define S3C2410_IISMOD_16BIT (1<<3) 42 #define S3C2410_IISMOD_BITMASK (1<<3) 43 #define S3C2410_IISMOD_256FS (0<<2) 44 #define S3C2410_IISMOD_384FS (1<<2) 45 #define S3C2410_IISMOD_16FS (0<<0) 46 #define S3C2410_IISMOD_32FS (1<<0) 47 #define S3C2410_IISMOD_48FS (2<<0) 48 #define S3C2410_IISMOD_FS_MASK (3<<0) 49 50 #define S3C2410_IISPSR (0x08) 51 #define S3C2410_IISPSR_INTMASK (31<<5) 52 #define S3C2410_IISPSR_INTSHIFT (5) 53 #define S3C2410_IISPSR_EXTMASK (31<<0) 54 #define S3C2410_IISPSR_EXTSHFIT (0) 55 56 #define S3C2410_IISFCON (0x0c) 57 58 #define S3C2410_IISFCON_TXDMA (1<<15) 59 #define S3C2410_IISFCON_RXDMA (1<<14) 60 #define S3C2410_IISFCON_TXENABLE (1<<13) 61 #define S3C2410_IISFCON_RXENABLE (1<<12) 62 #define S3C2410_IISFCON_TXMASK (0x3f << 6) 63 #define S3C2410_IISFCON_TXSHIFT (6) 64 #define S3C2410_IISFCON_RXMASK (0x3f) 65 #define S3C2410_IISFCON_RXSHIFT (0) 66 67 #define S3C2400_IISFCON_TXDMA (1<<11) 68 #define S3C2400_IISFCON_RXDMA (1<<10) 69 #define S3C2400_IISFCON_TXENABLE (1<<9) 70 #define S3C2400_IISFCON_RXENABLE (1<<8) 71 #define S3C2400_IISFCON_TXMASK (0x07 << 4) 72 #define S3C2400_IISFCON_TXSHIFT (4) 73 #define S3C2400_IISFCON_RXMASK (0x07) 74 #define S3C2400_IISFCON_RXSHIFT (0) 75 76 #define S3C2410_IISFIFO (0x10) 77 #endif /* __ASM_ARCH_REGS_IIS_H */ 78