1 /* 2 * Copyright (c) 2009, Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 */ 17 #ifndef __PSB_INTEL_REG_H__ 18 #define __PSB_INTEL_REG_H__ 19 20 #define BLC_PWM_CTL 0x61254 21 #define BLC_PWM_CTL2 0x61250 22 #define BLC_PWM_CTL_C 0x62254 23 #define BLC_PWM_CTL2_C 0x62250 24 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 25 /* 26 * This is the most significant 15 bits of the number of backlight cycles in a 27 * complete cycle of the modulated backlight control. 28 * 29 * The actual value is this field multiplied by two. 30 */ 31 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 32 #define BLM_LEGACY_MODE (1 << 16) 33 /* 34 * This is the number of cycles out of the backlight modulation cycle for which 35 * the backlight is on. 36 * 37 * This field must be no greater than the number of cycles in the complete 38 * backlight modulation cycle. 39 */ 40 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 41 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 42 43 #define I915_GCFGC 0xf0 44 #define I915_LOW_FREQUENCY_ENABLE (1 << 7) 45 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 46 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 47 #define I915_DISPLAY_CLOCK_MASK (7 << 4) 48 49 #define I855_HPLLCC 0xc0 50 #define I855_CLOCK_CONTROL_MASK (3 << 0) 51 #define I855_CLOCK_133_200 (0 << 0) 52 #define I855_CLOCK_100_200 (1 << 0) 53 #define I855_CLOCK_100_133 (2 << 0) 54 #define I855_CLOCK_166_250 (3 << 0) 55 56 /* I830 CRTC registers */ 57 #define HTOTAL_A 0x60000 58 #define HBLANK_A 0x60004 59 #define HSYNC_A 0x60008 60 #define VTOTAL_A 0x6000c 61 #define VBLANK_A 0x60010 62 #define VSYNC_A 0x60014 63 #define PIPEASRC 0x6001c 64 #define BCLRPAT_A 0x60020 65 #define VSYNCSHIFT_A 0x60028 66 67 #define HTOTAL_B 0x61000 68 #define HBLANK_B 0x61004 69 #define HSYNC_B 0x61008 70 #define VTOTAL_B 0x6100c 71 #define VBLANK_B 0x61010 72 #define VSYNC_B 0x61014 73 #define PIPEBSRC 0x6101c 74 #define BCLRPAT_B 0x61020 75 #define VSYNCSHIFT_B 0x61028 76 77 #define HTOTAL_C 0x62000 78 #define HBLANK_C 0x62004 79 #define HSYNC_C 0x62008 80 #define VTOTAL_C 0x6200c 81 #define VBLANK_C 0x62010 82 #define VSYNC_C 0x62014 83 #define PIPECSRC 0x6201c 84 #define BCLRPAT_C 0x62020 85 #define VSYNCSHIFT_C 0x62028 86 87 #define PP_STATUS 0x61200 88 # define PP_ON (1 << 31) 89 /* 90 * Indicates that all dependencies of the panel are on: 91 * 92 * - PLL enabled 93 * - pipe enabled 94 * - LVDS/DVOB/DVOC on 95 */ 96 # define PP_READY (1 << 30) 97 # define PP_SEQUENCE_NONE (0 << 28) 98 # define PP_SEQUENCE_ON (1 << 28) 99 # define PP_SEQUENCE_OFF (2 << 28) 100 # define PP_SEQUENCE_MASK 0x30000000 101 #define PP_CONTROL 0x61204 102 # define POWER_TARGET_ON (1 << 0) 103 104 #define LVDSPP_ON 0x61208 105 #define LVDSPP_OFF 0x6120c 106 #define PP_CYCLE 0x61210 107 108 #define PFIT_CONTROL 0x61230 109 # define PFIT_ENABLE (1 << 31) 110 # define PFIT_PIPE_MASK (3 << 29) 111 # define PFIT_PIPE_SHIFT 29 112 # define PFIT_SCALING_MODE_PILLARBOX (1 << 27) 113 # define PFIT_SCALING_MODE_LETTERBOX (3 << 26) 114 # define VERT_INTERP_DISABLE (0 << 10) 115 # define VERT_INTERP_BILINEAR (1 << 10) 116 # define VERT_INTERP_MASK (3 << 10) 117 # define VERT_AUTO_SCALE (1 << 9) 118 # define HORIZ_INTERP_DISABLE (0 << 6) 119 # define HORIZ_INTERP_BILINEAR (1 << 6) 120 # define HORIZ_INTERP_MASK (3 << 6) 121 # define HORIZ_AUTO_SCALE (1 << 5) 122 # define PANEL_8TO6_DITHER_ENABLE (1 << 3) 123 124 #define PFIT_PGM_RATIOS 0x61234 125 # define PFIT_VERT_SCALE_MASK 0xfff00000 126 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0 127 128 #define PFIT_AUTO_RATIOS 0x61238 129 130 131 #define DPLL_A 0x06014 132 #define DPLL_B 0x06018 133 # define DPLL_VCO_ENABLE (1 << 31) 134 # define DPLL_DVO_HIGH_SPEED (1 << 30) 135 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 136 # define DPLL_VGA_MODE_DIS (1 << 28) 137 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 138 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 139 # define DPLL_MODE_MASK (3 << 26) 140 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 141 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 142 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 143 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 144 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 145 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 146 /* 147 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 148 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 149 */ 150 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 151 /* 152 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 153 * this field (only one bit may be set). 154 */ 155 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 156 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 157 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required 158 * in DVO non-gang */ 159 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 160 # define PLL_REF_INPUT_DREFCLK (0 << 13) 161 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 162 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO 163 * TVCLKIN */ 164 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 165 # define PLL_REF_INPUT_MASK (3 << 13) 166 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 167 /* 168 * Parallel to Serial Load Pulse phase selection. 169 * Selects the phase for the 10X DPLL clock for the PCIe 170 * digital display port. The range is 4 to 13; 10 or more 171 * is just a flip delay. The default is 6 172 */ 173 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 174 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 175 176 /* 177 * SDVO multiplier for 945G/GM. Not used on 965. 178 * 179 * DPLL_MD_UDI_MULTIPLIER_MASK 180 */ 181 # define SDVO_MULTIPLIER_MASK 0x000000ff 182 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 183 # define SDVO_MULTIPLIER_SHIFT_VGA 0 184 185 /* 186 * PLL_MD 187 */ 188 /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 189 #define DPLL_A_MD 0x0601c 190 /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 191 #define DPLL_B_MD 0x06020 192 /* 193 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 194 * 195 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 196 */ 197 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 198 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 199 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 200 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 201 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 202 /* 203 * SDVO/UDI pixel multiplier. 204 * 205 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 206 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 207 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 208 * dummy bytes in the datastream at an increased clock rate, with both sides of 209 * the link knowing how many bytes are fill. 210 * 211 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 212 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 213 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 214 * through an SDVO command. 215 * 216 * This register field has values of multiplication factor minus 1, with 217 * a maximum multiplier of 5 for SDVO. 218 */ 219 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 220 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 221 /* 222 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 223 * This best be set to the default value (3) or the CRT won't work. No, 224 * I don't entirely understand what this does... 225 */ 226 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 227 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 228 229 #define DPLL_TEST 0x606c 230 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 231 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 232 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 233 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 234 # define DPLLB_TEST_N_BYPASS (1 << 19) 235 # define DPLLB_TEST_M_BYPASS (1 << 18) 236 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 237 # define DPLLA_TEST_N_BYPASS (1 << 3) 238 # define DPLLA_TEST_M_BYPASS (1 << 2) 239 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 240 241 #define ADPA 0x61100 242 #define ADPA_DAC_ENABLE (1<<31) 243 #define ADPA_DAC_DISABLE 0 244 #define ADPA_PIPE_SELECT_MASK (1<<30) 245 #define ADPA_PIPE_A_SELECT 0 246 #define ADPA_PIPE_B_SELECT (1<<30) 247 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 248 #define ADPA_SETS_HVPOLARITY 0 249 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 250 #define ADPA_VSYNC_CNTL_ENABLE 0 251 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 252 #define ADPA_HSYNC_CNTL_ENABLE 0 253 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 254 #define ADPA_VSYNC_ACTIVE_LOW 0 255 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 256 #define ADPA_HSYNC_ACTIVE_LOW 0 257 258 #define FPA0 0x06040 259 #define FPA1 0x06044 260 #define FPB0 0x06048 261 #define FPB1 0x0604c 262 # define FP_N_DIV_MASK 0x003f0000 263 # define FP_N_DIV_SHIFT 16 264 # define FP_M1_DIV_MASK 0x00003f00 265 # define FP_M1_DIV_SHIFT 8 266 # define FP_M2_DIV_MASK 0x0000003f 267 # define FP_M2_DIV_SHIFT 0 268 269 270 #define PORT_HOTPLUG_EN 0x61110 271 # define SDVOB_HOTPLUG_INT_EN (1 << 26) 272 # define SDVOC_HOTPLUG_INT_EN (1 << 25) 273 # define TV_HOTPLUG_INT_EN (1 << 18) 274 # define CRT_HOTPLUG_INT_EN (1 << 9) 275 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 276 277 #define PORT_HOTPLUG_STAT 0x61114 278 # define CRT_HOTPLUG_INT_STATUS (1 << 11) 279 # define TV_HOTPLUG_INT_STATUS (1 << 10) 280 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 281 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 282 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 283 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 284 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 285 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 286 287 #define SDVOB 0x61140 288 #define SDVOC 0x61160 289 #define SDVO_ENABLE (1 << 31) 290 #define SDVO_PIPE_B_SELECT (1 << 30) 291 #define SDVO_STALL_SELECT (1 << 29) 292 #define SDVO_INTERRUPT_ENABLE (1 << 26) 293 /** 294 * 915G/GM SDVO pixel multiplier. 295 * 296 * Programmed value is multiplier - 1, up to 5x. 297 * 298 * DPLL_MD_UDI_MULTIPLIER_MASK 299 */ 300 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 301 #define SDVO_PORT_MULTIPLY_SHIFT 23 302 #define SDVO_PHASE_SELECT_MASK (15 << 19) 303 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 304 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 305 #define SDVOC_GANG_MODE (1 << 16) 306 #define SDVO_BORDER_ENABLE (1 << 7) 307 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 308 #define SDVO_DETECTED (1 << 2) 309 /* Bits to be preserved when writing */ 310 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 311 #define SDVOC_PRESERVE_MASK (1 << 17) 312 313 /* 314 * This register controls the LVDS output enable, pipe selection, and data 315 * format selection. 316 * 317 * All of the clock/data pairs are force powered down by power sequencing. 318 */ 319 #define LVDS 0x61180 320 /* 321 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 322 * the DPLL semantics change when the LVDS is assigned to that pipe. 323 */ 324 # define LVDS_PORT_EN (1 << 31) 325 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 326 # define LVDS_PIPEB_SELECT (1 << 30) 327 328 /* Turns on border drawing to allow centered display. */ 329 # define LVDS_BORDER_EN (1 << 15) 330 331 /* 332 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 333 * pixel. 334 */ 335 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 336 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 337 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 338 /* 339 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 340 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 341 * on. 342 */ 343 # define LVDS_A3_POWER_MASK (3 << 6) 344 # define LVDS_A3_POWER_DOWN (0 << 6) 345 # define LVDS_A3_POWER_UP (3 << 6) 346 /* 347 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 348 * is set. 349 */ 350 # define LVDS_CLKB_POWER_MASK (3 << 4) 351 # define LVDS_CLKB_POWER_DOWN (0 << 4) 352 # define LVDS_CLKB_POWER_UP (3 << 4) 353 /* 354 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 355 * setting for whether we are in dual-channel mode. The B3 pair will 356 * additionally only be powered up when LVDS_A3_POWER_UP is set. 357 */ 358 # define LVDS_B0B3_POWER_MASK (3 << 2) 359 # define LVDS_B0B3_POWER_DOWN (0 << 2) 360 # define LVDS_B0B3_POWER_UP (3 << 2) 361 362 #define PIPEACONF 0x70008 363 #define PIPEACONF_ENABLE (1<<31) 364 #define PIPEACONF_DISABLE 0 365 #define PIPEACONF_DOUBLE_WIDE (1<<30) 366 #define PIPECONF_ACTIVE (1<<30) 367 #define I965_PIPECONF_ACTIVE (1<<30) 368 #define PIPECONF_DSIPLL_LOCK (1<<29) 369 #define PIPEACONF_SINGLE_WIDE 0 370 #define PIPEACONF_PIPE_UNLOCKED 0 371 #define PIPEACONF_DSR (1<<26) 372 #define PIPEACONF_PIPE_LOCKED (1<<25) 373 #define PIPEACONF_PALETTE 0 374 #define PIPECONF_FORCE_BORDER (1<<25) 375 #define PIPEACONF_GAMMA (1<<24) 376 #define PIPECONF_PROGRESSIVE (0 << 21) 377 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 378 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 379 #define PIPECONF_PLANE_OFF (1<<19) 380 #define PIPECONF_CURSOR_OFF (1<<18) 381 382 383 #define PIPEBCONF 0x71008 384 #define PIPEBCONF_ENABLE (1<<31) 385 #define PIPEBCONF_DISABLE 0 386 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 387 #define PIPEBCONF_DISABLE 0 388 #define PIPEBCONF_GAMMA (1<<24) 389 #define PIPEBCONF_PALETTE 0 390 391 #define PIPECCONF 0x72008 392 393 #define PIPEBGCMAXRED 0x71010 394 #define PIPEBGCMAXGREEN 0x71014 395 #define PIPEBGCMAXBLUE 0x71018 396 397 #define PIPEASTAT 0x70024 398 #define PIPEBSTAT 0x71024 399 #define PIPECSTAT 0x72024 400 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 401 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) 402 #define PIPE_VBLANK_CLEAR (1 << 1) 403 #define PIPE_VBLANK_STATUS (1 << 1) 404 #define PIPE_TE_STATUS (1UL<<6) 405 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 406 #define PIPE_VSYNC_CLEAR (1UL<<9) 407 #define PIPE_VSYNC_STATUS (1UL<<9) 408 #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL<<10) 409 #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL<<11) 410 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 411 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) 412 #define PIPE_TE_ENABLE (1UL<<22) 413 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 414 #define PIPE_VSYNC_ENABL (1UL<<25) 415 #define PIPE_HDMI_AUDIO_UNDERRUN (1UL<<26) 416 #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL<<27) 417 #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | PIPE_HDMI_AUDIO_BUFFER_DONE) 418 #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) 419 #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) 420 #define HISTOGRAM_INT_CONTROL 0x61268 421 #define HISTOGRAM_BIN_DATA 0X61264 422 #define HISTOGRAM_LOGIC_CONTROL 0x61260 423 #define PWM_CONTROL_LOGIC 0x61250 424 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 425 #define HISTOGRAM_INTERRUPT_ENABLE (1UL<<31) 426 #define HISTOGRAM_LOGIC_ENABLE (1UL<<31) 427 #define PWM_LOGIC_ENABLE (1UL<<31) 428 #define PWM_PHASEIN_ENABLE (1UL<<25) 429 #define PWM_PHASEIN_INT_ENABLE (1UL<<24) 430 #define PWM_PHASEIN_VB_COUNT 0x00001f00 431 #define PWM_PHASEIN_INC 0x0000001f 432 #define HISTOGRAM_INT_CTRL_CLEAR (1UL<<30) 433 #define DPST_YUV_LUMA_MODE 0 434 435 struct dpst_ie_histogram_control { 436 union { 437 uint32_t data; 438 struct { 439 uint32_t bin_reg_index:7; 440 uint32_t reserved:4; 441 uint32_t bin_reg_func_select:1; 442 uint32_t sync_to_phase_in:1; 443 uint32_t alt_enhancement_mode:2; 444 uint32_t reserved1:1; 445 uint32_t sync_to_phase_in_count:8; 446 uint32_t histogram_mode_select:1; 447 uint32_t reserved2:4; 448 uint32_t ie_pipe_assignment:1; 449 uint32_t ie_mode_table_enabled:1; 450 uint32_t ie_histogram_enable:1; 451 }; 452 }; 453 }; 454 455 struct dpst_guardband { 456 union { 457 uint32_t data; 458 struct { 459 uint32_t guardband:22; 460 uint32_t guardband_interrupt_delay:8; 461 uint32_t interrupt_status:1; 462 uint32_t interrupt_enable:1; 463 }; 464 }; 465 }; 466 467 #define PIPEAFRAMEHIGH 0x70040 468 #define PIPEAFRAMEPIXEL 0x70044 469 #define PIPEBFRAMEHIGH 0x71040 470 #define PIPEBFRAMEPIXEL 0x71044 471 #define PIPECFRAMEHIGH 0x72040 472 #define PIPECFRAMEPIXEL 0x72044 473 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 474 #define PIPE_FRAME_HIGH_SHIFT 0 475 #define PIPE_FRAME_LOW_MASK 0xff000000 476 #define PIPE_FRAME_LOW_SHIFT 24 477 #define PIPE_PIXEL_MASK 0x00ffffff 478 #define PIPE_PIXEL_SHIFT 0 479 480 #define DSPARB 0x70030 481 #define DSPFW1 0x70034 482 #define DSPFW2 0x70038 483 #define DSPFW3 0x7003c 484 #define DSPFW4 0x70050 485 #define DSPFW5 0x70054 486 #define DSPFW6 0x70058 487 #define DSPCHICKENBIT 0x70400 488 #define DSPACNTR 0x70180 489 #define DSPBCNTR 0x71180 490 #define DSPCCNTR 0x72180 491 #define DISPLAY_PLANE_ENABLE (1<<31) 492 #define DISPLAY_PLANE_DISABLE 0 493 #define DISPPLANE_GAMMA_ENABLE (1<<30) 494 #define DISPPLANE_GAMMA_DISABLE 0 495 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 496 #define DISPPLANE_8BPP (0x2<<26) 497 #define DISPPLANE_15_16BPP (0x4<<26) 498 #define DISPPLANE_16BPP (0x5<<26) 499 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 500 #define DISPPLANE_32BPP (0x7<<26) 501 #define DISPPLANE_STEREO_ENABLE (1<<25) 502 #define DISPPLANE_STEREO_DISABLE 0 503 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 504 #define DISPPLANE_SEL_PIPE_POS 24 505 #define DISPPLANE_SEL_PIPE_A 0 506 #define DISPPLANE_SEL_PIPE_B (1<<24) 507 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 508 #define DISPPLANE_SRC_KEY_DISABLE 0 509 #define DISPPLANE_LINE_DOUBLE (1<<20) 510 #define DISPPLANE_NO_LINE_DOUBLE 0 511 #define DISPPLANE_STEREO_POLARITY_FIRST 0 512 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 513 /* plane B only */ 514 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 515 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 516 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 517 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 518 #define DISPPLANE_BOTTOM (4) 519 520 #define DSPABASE 0x70184 521 #define DSPALINOFF 0x70184 522 #define DSPASTRIDE 0x70188 523 524 #define DSPBBASE 0x71184 525 #define DSPBLINOFF 0X71184 526 #define DSPBADDR DSPBBASE 527 #define DSPBSTRIDE 0x71188 528 529 #define DSPCBASE 0x72184 530 #define DSPCLINOFF 0x72184 531 #define DSPCSTRIDE 0x72188 532 533 #define DSPAKEYVAL 0x70194 534 #define DSPAKEYMASK 0x70198 535 536 #define DSPAPOS 0x7018C /* reserved */ 537 #define DSPASIZE 0x70190 538 #define DSPBPOS 0x7118C 539 #define DSPBSIZE 0x71190 540 #define DSPCPOS 0x7218C 541 #define DSPCSIZE 0x72190 542 543 #define DSPASURF 0x7019C 544 #define DSPATILEOFF 0x701A4 545 546 #define DSPBSURF 0x7119C 547 #define DSPBTILEOFF 0x711A4 548 549 #define DSPCSURF 0x7219C 550 #define DSPCTILEOFF 0x721A4 551 #define DSPCKEYMAXVAL 0x721A0 552 #define DSPCKEYMINVAL 0x72194 553 #define DSPCKEYMSK 0x72198 554 555 #define VGACNTRL 0x71400 556 # define VGA_DISP_DISABLE (1 << 31) 557 # define VGA_2X_MODE (1 << 30) 558 # define VGA_PIPE_B_SELECT (1 << 29) 559 560 /* 561 * Overlay registers 562 */ 563 #define OV_C_OFFSET 0x08000 564 #define OV_OVADD 0x30000 565 #define OV_DOVASTA 0x30008 566 # define OV_PIPE_SELECT ((1 << 6)|(1 << 7)) 567 # define OV_PIPE_SELECT_POS 6 568 # define OV_PIPE_A 0 569 # define OV_PIPE_C 1 570 #define OV_OGAMC5 0x30010 571 #define OV_OGAMC4 0x30014 572 #define OV_OGAMC3 0x30018 573 #define OV_OGAMC2 0x3001C 574 #define OV_OGAMC1 0x30020 575 #define OV_OGAMC0 0x30024 576 #define OVC_OVADD 0x38000 577 #define OVC_DOVCSTA 0x38008 578 #define OVC_OGAMC5 0x38010 579 #define OVC_OGAMC4 0x38014 580 #define OVC_OGAMC3 0x38018 581 #define OVC_OGAMC2 0x3801C 582 #define OVC_OGAMC1 0x38020 583 #define OVC_OGAMC0 0x38024 584 585 /* 586 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 587 * of video memory available to the BIOS in SWF1. 588 */ 589 #define SWF0 0x71410 590 #define SWF1 0x71414 591 #define SWF2 0x71418 592 #define SWF3 0x7141c 593 #define SWF4 0x71420 594 #define SWF5 0x71424 595 #define SWF6 0x71428 596 597 /* 598 * 855 scratch registers. 599 */ 600 #define SWF00 0x70410 601 #define SWF01 0x70414 602 #define SWF02 0x70418 603 #define SWF03 0x7041c 604 #define SWF04 0x70420 605 #define SWF05 0x70424 606 #define SWF06 0x70428 607 608 #define SWF10 SWF0 609 #define SWF11 SWF1 610 #define SWF12 SWF2 611 #define SWF13 SWF3 612 #define SWF14 SWF4 613 #define SWF15 SWF5 614 #define SWF16 SWF6 615 616 #define SWF30 0x72414 617 #define SWF31 0x72418 618 #define SWF32 0x7241c 619 620 621 /* 622 * Palette registers 623 */ 624 #define PALETTE_A 0x0a000 625 #define PALETTE_B 0x0a800 626 #define PALETTE_C 0x0ac00 627 628 /* Cursor A & B regs */ 629 #define CURACNTR 0x70080 630 #define CURSOR_MODE_DISABLE 0x00 631 #define CURSOR_MODE_64_32B_AX 0x07 632 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 633 #define MCURSOR_GAMMA_ENABLE (1 << 26) 634 #define CURABASE 0x70084 635 #define CURAPOS 0x70088 636 #define CURSOR_POS_MASK 0x007FF 637 #define CURSOR_POS_SIGN 0x8000 638 #define CURSOR_X_SHIFT 0 639 #define CURSOR_Y_SHIFT 16 640 #define CURBCNTR 0x700c0 641 #define CURBBASE 0x700c4 642 #define CURBPOS 0x700c8 643 #define CURCCNTR 0x700e0 644 #define CURCBASE 0x700e4 645 #define CURCPOS 0x700e8 646 647 /* 648 * Interrupt Registers 649 */ 650 #define IER 0x020a0 651 #define IIR 0x020a4 652 #define IMR 0x020a8 653 #define ISR 0x020ac 654 655 /* 656 * MOORESTOWN delta registers 657 */ 658 #define MRST_DPLL_A 0x0f014 659 #define MDFLD_DPLL_B 0x0f018 660 #define MDFLD_INPUT_REF_SEL (1 << 14) 661 #define MDFLD_VCO_SEL (1 << 16) 662 #define DPLLA_MODE_LVDS (2 << 26) /* mrst */ 663 #define MDFLD_PLL_LATCHEN (1 << 28) 664 #define MDFLD_PWR_GATE_EN (1 << 30) 665 #define MDFLD_P1_MASK (0x1FF << 17) 666 #define MRST_FPA0 0x0f040 667 #define MRST_FPA1 0x0f044 668 #define MDFLD_DPLL_DIV0 0x0f048 669 #define MDFLD_DPLL_DIV1 0x0f04c 670 #define MRST_PERF_MODE 0x020f4 671 672 /* 673 * MEDFIELD HDMI registers 674 */ 675 #define HDMIPHYMISCCTL 0x61134 676 # define HDMI_PHY_POWER_DOWN 0x7f 677 #define HDMIB_CONTROL 0x61140 678 # define HDMIB_PORT_EN (1 << 31) 679 # define HDMIB_PIPE_B_SELECT (1 << 30) 680 # define HDMIB_NULL_PACKET (1 << 9) 681 #define HDMIB_HDCP_PORT (1 << 5) 682 683 /* #define LVDS 0x61180 */ 684 # define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) 685 # define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) 686 # define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) 687 688 #define MIPI 0x61190 689 #define MIPI_C 0x62190 690 # define MIPI_PORT_EN (1 << 31) 691 /* Turns on border drawing to allow centered display. */ 692 # define SEL_FLOPPED_HSTX (1 << 23) 693 # define PASS_FROM_SPHY_TO_AFE (1 << 16) 694 # define MIPI_BORDER_EN (1 << 15) 695 # define MIPIA_3LANE_MIPIC_1LANE 0x1 696 # define MIPIA_2LANE_MIPIC_2LANE 0x2 697 # define TE_TRIGGER_DSI_PROTOCOL (1 << 2) 698 # define TE_TRIGGER_GPIO_PIN (1 << 3) 699 #define MIPI_TE_COUNT 0x61194 700 701 /* #define PP_CONTROL 0x61204 */ 702 # define POWER_DOWN_ON_RESET (1 << 1) 703 704 /* #define PFIT_CONTROL 0x61230 */ 705 # define PFIT_PIPE_SELECT (3 << 29) 706 # define PFIT_PIPE_SELECT_SHIFT (29) 707 708 /* #define BLC_PWM_CTL 0x61254 */ 709 #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) 710 #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) 711 712 /* #define PIPEACONF 0x70008 */ 713 #define PIPEACONF_PIPE_STATE (1<<30) 714 /* #define DSPACNTR 0x70180 */ 715 716 #define MRST_DSPABASE 0x7019c 717 #define MRST_DSPBBASE 0x7119c 718 #define MDFLD_DSPCBASE 0x7219c 719 720 /* 721 * Moorestown registers. 722 */ 723 724 /* 725 * MIPI IP registers 726 */ 727 #define MIPIC_REG_OFFSET 0x800 728 #define DEVICE_READY_REG 0xb000 729 #define LP_OUTPUT_HOLD (1 << 16) 730 #define EXIT_ULPS_DEV_READY 0x3 731 #define LP_OUTPUT_HOLD_RELEASE 0x810000 732 # define ENTERING_ULPS (2 << 1) 733 # define EXITING_ULPS (1 << 1) 734 # define ULPS_MASK (3 << 1) 735 # define BUS_POSSESSION (1 << 3) 736 #define INTR_STAT_REG 0xb004 737 #define RX_SOT_ERROR (1 << 0) 738 #define RX_SOT_SYNC_ERROR (1 << 1) 739 #define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3) 740 #define RX_LP_TX_SYNC_ERROR (1 << 4) 741 #define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5) 742 #define RX_FALSE_CONTROL_ERROR (1 << 6) 743 #define RX_ECC_SINGLE_BIT_ERROR (1 << 7) 744 #define RX_ECC_MULTI_BIT_ERROR (1 << 8) 745 #define RX_CHECKSUM_ERROR (1 << 9) 746 #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10) 747 #define RX_DSI_VC_ID_INVALID (1 << 11) 748 #define TX_FALSE_CONTROL_ERROR (1 << 12) 749 #define TX_ECC_SINGLE_BIT_ERROR (1 << 13) 750 #define TX_ECC_MULTI_BIT_ERROR (1 << 14) 751 #define TX_CHECKSUM_ERROR (1 << 15) 752 #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16) 753 #define TX_DSI_VC_ID_INVALID (1 << 17) 754 #define HIGH_CONTENTION (1 << 18) 755 #define LOW_CONTENTION (1 << 19) 756 #define DPI_FIFO_UNDER_RUN (1 << 20) 757 #define HS_TX_TIMEOUT (1 << 21) 758 #define LP_RX_TIMEOUT (1 << 22) 759 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 760 #define ACK_WITH_NO_ERROR (1 << 24) 761 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 762 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 763 #define SPL_PKT_SENT (1 << 30) 764 #define INTR_EN_REG 0xb008 765 #define DSI_FUNC_PRG_REG 0xb00c 766 #define DPI_CHANNEL_NUMBER_POS 0x03 767 #define DBI_CHANNEL_NUMBER_POS 0x05 768 #define FMT_DPI_POS 0x07 769 #define FMT_DBI_POS 0x0A 770 #define DBI_DATA_WIDTH_POS 0x0D 771 /* DPI PIXEL FORMATS */ 772 #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ 773 #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ 774 #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED 775 * 666 FORMAT 776 */ 777 #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ 778 #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ 779 #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ 780 #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ 781 #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ 782 #define DBI_NOT_SUPPORTED 0x00 /* command mode 783 * is not supported 784 */ 785 #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ 786 #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ 787 #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ 788 #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ 789 #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ 790 #define HS_TX_TIMEOUT_REG 0xb010 791 #define LP_RX_TIMEOUT_REG 0xb014 792 #define TURN_AROUND_TIMEOUT_REG 0xb018 793 #define DEVICE_RESET_REG 0xb01C 794 #define DPI_RESOLUTION_REG 0xb020 795 #define RES_V_POS 0x10 796 #define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */ 797 #define HORIZ_SYNC_PAD_COUNT_REG 0xb028 798 #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C 799 #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 800 #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 801 #define VERT_SYNC_PAD_COUNT_REG 0xb038 802 #define VERT_BACK_PORCH_COUNT_REG 0xb03c 803 #define VERT_FRONT_PORCH_COUNT_REG 0xb040 804 #define HIGH_LOW_SWITCH_COUNT_REG 0xb044 805 #define DPI_CONTROL_REG 0xb048 806 #define DPI_SHUT_DOWN (1 << 0) 807 #define DPI_TURN_ON (1 << 1) 808 #define DPI_COLOR_MODE_ON (1 << 2) 809 #define DPI_COLOR_MODE_OFF (1 << 3) 810 #define DPI_BACK_LIGHT_ON (1 << 4) 811 #define DPI_BACK_LIGHT_OFF (1 << 5) 812 #define DPI_LP (1 << 6) 813 #define DPI_DATA_REG 0xb04c 814 #define DPI_BACK_LIGHT_ON_DATA 0x07 815 #define DPI_BACK_LIGHT_OFF_DATA 0x17 816 #define INIT_COUNT_REG 0xb050 817 #define MAX_RET_PAK_REG 0xb054 818 #define VIDEO_FMT_REG 0xb058 819 #define COMPLETE_LAST_PCKT (1 << 2) 820 #define EOT_DISABLE_REG 0xb05c 821 #define ENABLE_CLOCK_STOPPING (1 << 1) 822 #define LP_BYTECLK_REG 0xb060 823 #define LP_GEN_DATA_REG 0xb064 824 #define HS_GEN_DATA_REG 0xb068 825 #define LP_GEN_CTRL_REG 0xb06C 826 #define HS_GEN_CTRL_REG 0xb070 827 #define DCS_CHANNEL_NUMBER_POS 0x06 828 #define MCS_COMMANDS_POS 0x8 829 #define WORD_COUNTS_POS 0x8 830 #define MCS_PARAMETER_POS 0x10 831 #define GEN_FIFO_STAT_REG 0xb074 832 #define HS_DATA_FIFO_FULL (1 << 0) 833 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 834 #define HS_DATA_FIFO_EMPTY (1 << 2) 835 #define LP_DATA_FIFO_FULL (1 << 8) 836 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 837 #define LP_DATA_FIFO_EMPTY (1 << 10) 838 #define HS_CTRL_FIFO_FULL (1 << 16) 839 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 840 #define HS_CTRL_FIFO_EMPTY (1 << 18) 841 #define LP_CTRL_FIFO_FULL (1 << 24) 842 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 843 #define LP_CTRL_FIFO_EMPTY (1 << 26) 844 #define DBI_FIFO_EMPTY (1 << 27) 845 #define DPI_FIFO_EMPTY (1 << 28) 846 #define HS_LS_DBI_ENABLE_REG 0xb078 847 #define TXCLKESC_REG 0xb07c 848 #define DPHY_PARAM_REG 0xb080 849 #define DBI_BW_CTRL_REG 0xb084 850 #define CLK_LANE_SWT_REG 0xb088 851 852 /* 853 * MIPI Adapter registers 854 */ 855 #define MIPI_CONTROL_REG 0xb104 856 #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) 857 #define MIPI_DATA_ADDRESS_REG 0xb108 858 #define MIPI_DATA_LENGTH_REG 0xb10C 859 #define MIPI_COMMAND_ADDRESS_REG 0xb110 860 #define MIPI_COMMAND_LENGTH_REG 0xb114 861 #define MIPI_READ_DATA_RETURN_REG0 0xb118 862 #define MIPI_READ_DATA_RETURN_REG1 0xb11C 863 #define MIPI_READ_DATA_RETURN_REG2 0xb120 864 #define MIPI_READ_DATA_RETURN_REG3 0xb124 865 #define MIPI_READ_DATA_RETURN_REG4 0xb128 866 #define MIPI_READ_DATA_RETURN_REG5 0xb12C 867 #define MIPI_READ_DATA_RETURN_REG6 0xb130 868 #define MIPI_READ_DATA_RETURN_REG7 0xb134 869 #define MIPI_READ_DATA_VALID_REG 0xb138 870 /* DBI COMMANDS */ 871 #define soft_reset 0x01 872 /* 873 * The display module performs a software reset. 874 * Registers are written with their SW Reset default values. 875 */ 876 #define get_power_mode 0x0a 877 /* 878 * The display module returns the current power mode 879 */ 880 #define get_address_mode 0x0b 881 /* 882 * The display module returns the current status. 883 */ 884 #define get_pixel_format 0x0c 885 /* 886 * This command gets the pixel format for the RGB image data 887 * used by the interface. 888 */ 889 #define get_display_mode 0x0d 890 /* 891 * The display module returns the Display Image Mode status. 892 */ 893 #define get_signal_mode 0x0e 894 /* 895 * The display module returns the Display Signal Mode. 896 */ 897 #define get_diagnostic_result 0x0f 898 /* 899 * The display module returns the self-diagnostic results following 900 * a Sleep Out command. 901 */ 902 #define enter_sleep_mode 0x10 903 /* 904 * This command causes the display module to enter the Sleep mode. 905 * In this mode, all unnecessary blocks inside the display module are 906 * disabled except interface communication. This is the lowest power 907 * mode the display module supports. 908 */ 909 #define exit_sleep_mode 0x11 910 /* 911 * This command causes the display module to exit Sleep mode. 912 * All blocks inside the display module are enabled. 913 */ 914 #define enter_partial_mode 0x12 915 /* 916 * This command causes the display module to enter the Partial Display 917 * Mode. The Partial Display Mode window is described by the 918 * set_partial_area command. 919 */ 920 #define enter_normal_mode 0x13 921 /* 922 * This command causes the display module to enter the Normal mode. 923 * Normal Mode is defined as Partial Display mode and Scroll mode are off 924 */ 925 #define exit_invert_mode 0x20 926 /* 927 * This command causes the display module to stop inverting the image 928 * data on the display device. The frame memory contents remain unchanged. 929 * No status bits are changed. 930 */ 931 #define enter_invert_mode 0x21 932 /* 933 * This command causes the display module to invert the image data only on 934 * the display device. The frame memory contents remain unchanged. 935 * No status bits are changed. 936 */ 937 #define set_gamma_curve 0x26 938 /* 939 * This command selects the desired gamma curve for the display device. 940 * Four fixed gamma curves are defined in section DCS spec. 941 */ 942 #define set_display_off 0x28 943 /* ************************************************************************* *\ 944 This command causes the display module to stop displaying the image data 945 on the display device. The frame memory contents remain unchanged. 946 No status bits are changed. 947 \* ************************************************************************* */ 948 #define set_display_on 0x29 949 /* ************************************************************************* *\ 950 This command causes the display module to start displaying the image data 951 on the display device. The frame memory contents remain unchanged. 952 No status bits are changed. 953 \* ************************************************************************* */ 954 #define set_column_address 0x2a 955 /* 956 * This command defines the column extent of the frame memory accessed by 957 * the hostprocessor with the read_memory_continue and 958 * write_memory_continue commands. 959 * No status bits are changed. 960 */ 961 #define set_page_addr 0x2b 962 /* 963 * This command defines the page extent of the frame memory accessed by 964 * the host processor with the write_memory_continue and 965 * read_memory_continue command. 966 * No status bits are changed. 967 */ 968 #define write_mem_start 0x2c 969 /* 970 * This command transfers image data from the host processor to the 971 * display module s frame memory starting at the pixel location specified 972 * by preceding set_column_address and set_page_address commands. 973 */ 974 #define set_partial_area 0x30 975 /* 976 * This command defines the Partial Display mode s display area. 977 * There are two parameters associated with this command, the first 978 * defines the Start Row (SR) and the second the End Row (ER). SR and ER 979 * refer to the Frame Memory Line Pointer. 980 */ 981 #define set_scroll_area 0x33 982 /* 983 * This command defines the display modules Vertical Scrolling Area. 984 */ 985 #define set_tear_off 0x34 986 /* 987 * This command turns off the display modules Tearing Effect output 988 * signal on the TE signal line. 989 */ 990 #define set_tear_on 0x35 991 /* 992 * This command turns on the display modules Tearing Effect output signal 993 * on the TE signal line. 994 */ 995 #define set_address_mode 0x36 996 /* 997 * This command sets the data order for transfers from the host processor 998 * to display modules frame memory,bits B[7:5] and B3, and from the 999 * display modules frame memory to the display device, bits B[2:0] and B4. 1000 */ 1001 #define set_scroll_start 0x37 1002 /* 1003 * This command sets the start of the vertical scrolling area in the frame 1004 * memory. The vertical scrolling area is fully defined when this command 1005 * is used with the set_scroll_area command The set_scroll_start command 1006 * has one parameter, the Vertical Scroll Pointer. The VSP defines the 1007 * line in the frame memory that is written to the display device as the 1008 * first line of the vertical scroll area. 1009 */ 1010 #define exit_idle_mode 0x38 1011 /* 1012 * This command causes the display module to exit Idle mode. 1013 */ 1014 #define enter_idle_mode 0x39 1015 /* 1016 * This command causes the display module to enter Idle Mode. 1017 * In Idle Mode, color expression is reduced. Colors are shown on the 1018 * display device using the MSB of each of the R, G and B color 1019 * components in the frame memory 1020 */ 1021 #define set_pixel_format 0x3a 1022 /* 1023 * This command sets the pixel format for the RGB image data used by the 1024 * interface. 1025 * Bits D[6:4] DPI Pixel Format Definition 1026 * Bits D[2:0] DBI Pixel Format Definition 1027 * Bits D7 and D3 are not used. 1028 */ 1029 #define DCS_PIXEL_FORMAT_3bbp 0x1 1030 #define DCS_PIXEL_FORMAT_8bbp 0x2 1031 #define DCS_PIXEL_FORMAT_12bbp 0x3 1032 #define DCS_PIXEL_FORMAT_16bbp 0x5 1033 #define DCS_PIXEL_FORMAT_18bbp 0x6 1034 #define DCS_PIXEL_FORMAT_24bbp 0x7 1035 #define write_mem_cont 0x3c 1036 /* 1037 * This command transfers image data from the host processor to the 1038 * display module's frame memory continuing from the pixel location 1039 * following the previous write_memory_continue or write_memory_start 1040 * command. 1041 */ 1042 #define set_tear_scanline 0x44 1043 /* 1044 * This command turns on the display modules Tearing Effect output signal 1045 * on the TE signal line when the display module reaches line N. 1046 */ 1047 #define get_scanline 0x45 1048 /* 1049 * The display module returns the current scanline, N, used to update the 1050 * display device. The total number of scanlines on a display device is 1051 * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as 1052 * the first line of V Sync and is denoted as Line 0. 1053 * When in Sleep Mode, the value returned by get_scanline is undefined. 1054 */ 1055 1056 /* MCS or Generic COMMANDS */ 1057 /* MCS/generic data type */ 1058 #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */ 1059 #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */ 1060 #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */ 1061 #define GEN_READ_0 0x04 /* generic read, no parameters */ 1062 #define GEN_READ_1 0x14 /* generic read, 1 parameters */ 1063 #define GEN_READ_2 0x24 /* generic read, 2 parameters */ 1064 #define GEN_LONG_WRITE 0x29 /* generic long write */ 1065 #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */ 1066 #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */ 1067 #define MCS_READ 0x06 /* MCS read, no parameters */ 1068 #define MCS_LONG_WRITE 0x39 /* MCS long write */ 1069 /* MCS/generic commands */ 1070 /* TPO MCS */ 1071 #define write_display_profile 0x50 1072 #define write_display_brightness 0x51 1073 #define write_ctrl_display 0x53 1074 #define write_ctrl_cabc 0x55 1075 #define UI_IMAGE 0x01 1076 #define STILL_IMAGE 0x02 1077 #define MOVING_IMAGE 0x03 1078 #define write_hysteresis 0x57 1079 #define write_gamma_setting 0x58 1080 #define write_cabc_min_bright 0x5e 1081 #define write_kbbc_profile 0x60 1082 /* TMD MCS */ 1083 #define tmd_write_display_brightness 0x8c 1084 1085 /* 1086 * This command is used to control ambient light, panel backlight 1087 * brightness and gamma settings. 1088 */ 1089 #define BRIGHT_CNTL_BLOCK_ON (1 << 5) 1090 #define AMBIENT_LIGHT_SENSE_ON (1 << 4) 1091 #define DISPLAY_DIMMING_ON (1 << 3) 1092 #define BACKLIGHT_ON (1 << 2) 1093 #define DISPLAY_BRIGHTNESS_AUTO (1 << 1) 1094 #define GAMMA_AUTO (1 << 0) 1095 1096 /* DCS Interface Pixel Formats */ 1097 #define DCS_PIXEL_FORMAT_3BPP 0x1 1098 #define DCS_PIXEL_FORMAT_8BPP 0x2 1099 #define DCS_PIXEL_FORMAT_12BPP 0x3 1100 #define DCS_PIXEL_FORMAT_16BPP 0x5 1101 #define DCS_PIXEL_FORMAT_18BPP 0x6 1102 #define DCS_PIXEL_FORMAT_24BPP 0x7 1103 /* ONE PARAMETER READ DATA */ 1104 #define addr_mode_data 0xfc 1105 #define diag_res_data 0x00 1106 #define disp_mode_data 0x23 1107 #define pxl_fmt_data 0x77 1108 #define pwr_mode_data 0x74 1109 #define sig_mode_data 0x00 1110 /* TWO PARAMETERS READ DATA */ 1111 #define scanline_data1 0xff 1112 #define scanline_data2 0xff 1113 #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode 1114 * with Sync Pulse 1115 */ 1116 #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode 1117 * with Sync events 1118 */ 1119 #define BURST_MODE 0x03 /* Burst Mode */ 1120 #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ /* Allocate at least 1121 * 0x100 Byte with 32 1122 * byte alignment 1123 */ 1124 #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least 1125 * 0x100 Byte with 32 1126 * byte alignment 1127 */ 1128 #define DBI_CB_TIME_OUT 0xFFFF 1129 1130 #define GEN_FB_TIME_OUT 2000 1131 #define ALIGNMENT_32BYTE_MASK (~((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4))) 1132 #define SKU_83 0x01 1133 #define SKU_100 0x02 1134 #define SKU_100L 0x04 1135 #define SKU_BYPASS 0x08 1136 1137 #endif 1138