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Searched refs:REG_SET_BIT (Results 1 – 13 of 13) sorted by relevance

/linux-2.6.39/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c57 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
240 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
712 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
714 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
715 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
719 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
731 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
732 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
733 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
741 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
[all …]
Dar9002_hw.c438 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
492 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
494 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
497 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
522 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ar9002_hw_update_async_fifo()
536 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ar9002_hw_enable_wep_aggregation()
Dcalib.c208 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
215 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
218 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
257 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
Dbtcoex.c86 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
104 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_3wire()
Dmac.c152 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
153 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
154 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
705 REG_SET_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
748 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); in ath9k_hw_abortpcurecv()
961 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
Dhw.c989 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1336 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1367 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1508 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
1538 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
1583 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
1586 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
1595 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
1671 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
1711 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
[all …]
Dar9003_phy.c509 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
528 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
545 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
827 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1143 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
Dar5008_phy.c617 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
642 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
660 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
1112 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_old()
1279 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1575 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
Dar9003_hw.c367 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
Dar9003_calib.c57 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
302 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
Dar9002_phy.c431 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
Dar9003_paprd.c765 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve()
Dhw.h97 #define REG_SET_BIT(_a, _r, _f) \ macro