1 #ifndef __WINBOND_PHY_CALIBRATION_H 2 #define __WINBOND_PHY_CALIBRATION_H 3 4 #include "wbhal.h" 5 6 #define REG_AGC_CTRL1 0x1000 7 #define REG_AGC_CTRL2 0x1004 8 #define REG_AGC_CTRL3 0x1008 9 #define REG_AGC_CTRL4 0x100C 10 #define REG_AGC_CTRL5 0x1010 11 #define REG_AGC_CTRL6 0x1014 12 #define REG_AGC_CTRL7 0x1018 13 #define REG_AGC_CTRL8 0x101C 14 #define REG_AGC_CTRL9 0x1020 15 #define REG_AGC_CTRL10 0x1024 16 #define REG_CCA_CTRL 0x1028 17 #define REG_A_ACQ_CTRL 0x102C 18 #define REG_B_ACQ_CTRL 0x1030 19 #define REG_A_TXRX_CTRL 0x1034 20 #define REG_B_TXRX_CTRL 0x1038 21 #define REG_A_TX_COEF3 0x103C 22 #define REG_A_TX_COEF2 0x1040 23 #define REG_A_TX_COEF1 0x1044 24 #define REG_B_TX_COEF2 0x1048 25 #define REG_B_TX_COEF1 0x104C 26 #define REG_MODE_CTRL 0x1050 27 #define REG_CALIB_DATA 0x1054 28 #define REG_IQ_ALPHA 0x1058 29 #define REG_DC_CANCEL 0x105C 30 #define REG_WTO_READ 0x1060 31 #define REG_OFFSET_READ 0x1064 32 #define REG_CALIB_READ1 0x1068 33 #define REG_CALIB_READ2 0x106C 34 #define REG_A_FREQ_EST 0x1070 35 36 37 #define MASK_AMER_OFF_REG BIT(31) 38 39 #define MASK_BMER_OFF_REG BIT(31) 40 41 #define MASK_LNA_FIX_GAIN (BIT(3) | BIT(4)) 42 #define MASK_AGC_FIX BIT(1) 43 44 #define MASK_AGC_FIX_GAIN 0xFF00 45 46 #define MASK_ADC_DC_CAL_STR BIT(10) 47 #define MASK_CALIB_START BIT(4) 48 #define MASK_IQCAL_TONE_SEL (BIT(3) | BIT(2)) 49 #define MASK_IQCAL_MODE (BIT(1) | BIT(0)) 50 51 #define MASK_TX_CAL_0 0xF0000000 52 #define TX_CAL_0_SHIFT 28 53 #define MASK_TX_CAL_1 0x0F000000 54 #define TX_CAL_1_SHIFT 24 55 #define MASK_TX_CAL_2 0x00F00000 56 #define TX_CAL_2_SHIFT 20 57 #define MASK_TX_CAL_3 0x000F0000 58 #define TX_CAL_3_SHIFT 16 59 #define MASK_RX_CAL_0 0x0000F000 60 #define RX_CAL_0_SHIFT 12 61 #define MASK_RX_CAL_1 0x00000F00 62 #define RX_CAL_1_SHIFT 8 63 #define MASK_RX_CAL_2 0x000000F0 64 #define RX_CAL_2_SHIFT 4 65 #define MASK_RX_CAL_3 0x0000000F 66 #define RX_CAL_3_SHIFT 0 67 68 #define MASK_CANCEL_DC_I 0x3E0 69 #define CANCEL_DC_I_SHIFT 5 70 #define MASK_CANCEL_DC_Q 0x01F 71 #define CANCEL_DC_Q_SHIFT 0 72 73 #define MASK_ADC_DC_CAL_I(x) (((x) & 0x0003FE00) >> 9) 74 #define MASK_ADC_DC_CAL_Q(x) ((x) & 0x000001FF) 75 76 #define MASK_IQCAL_TONE_I 0x00001FFF 77 #define SHIFT_IQCAL_TONE_I(x) ((x) >> 0) 78 #define MASK_IQCAL_TONE_Q 0x03FFE000 79 #define SHIFT_IQCAL_TONE_Q(x) ((x) >> 13) 80 81 void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value); 82 #define phy_init_rf(_A) /* RFSynthesizer_initial(_A) */ 83 84 #endif 85