Searched refs:RD_REG_DWORD (Results 1 – 9 of 9) sorted by relevance
79 stat = RD_REG_DWORD(®->host_status); in qla24xx_dump_ram()92 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()98 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); in qla24xx_read_window()154 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && in qla24xx_pause_risc()176 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()197 if ((RD_REG_DWORD(®->ctrl_status) & in qla24xx_soft_reset()204 RD_REG_DWORD(®->hccr); /* PCI Posting. */ in qla24xx_soft_reset()253 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2xxx_dump_ram()371 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); in qla25xx_copy_mq()[all …]
461 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && in qla24xx_read_flash_dword()473 data = RD_REG_DWORD(®->flash_data); in qla24xx_read_flash_dword()501 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ in qla24xx_write_flash_dword()505 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && in qla24xx_write_flash_dword()1049 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1050 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1088 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1089 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_protect_flash()1314 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1315 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
156 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2300_intr_handler()2047 RD_REG_DWORD(®->iobase_addr); in qla2xxx_check_risc_status()2049 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()2061 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()2073 if (RD_REG_DWORD(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()2078 RD_REG_DWORD(®->iobase_window); in qla2xxx_check_risc_status()2121 stat = RD_REG_DWORD(®->host_status); in qla24xx_intr_handler()2126 hccr = RD_REG_DWORD(®->hccr); in qla24xx_intr_handler()2265 stat = RD_REG_DWORD(®->host_status); in qla24xx_msix_default()2270 hccr = RD_REG_DWORD(®->hccr); in qla24xx_msix_default()
359 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_pci_set_crbwindow_2M()496 data = RD_REG_DWORD((void __iomem *)off); in qla82xx_rd_32()2035 if (RD_REG_DWORD(®->host_int)) { in qla82xx_intr_handler()2036 stat = RD_REG_DWORD(®->host_status); in qla82xx_intr_handler()2109 if (RD_REG_DWORD(®->host_int)) { in qla82xx_msix_default()2110 stat = RD_REG_DWORD(®->host_status); in qla82xx_msix_default()2206 if (RD_REG_DWORD(®->host_int)) { in qla82xx_poll()2207 stat = RD_REG_DWORD(®->host_status); in qla82xx_poll()2915 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()3212 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_iocbs()
575 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { in qla2x00_isp_cmd()584 RD_REG_DWORD(&ioreg->hccr); in qla2x00_isp_cmd()1596 cnt = RD_REG_DWORD(®->isp25mq.req_q_out); in qla2x00_alloc_iocbs()1598 cnt = RD_REG_DWORD(®->isp82.req_q_out); in qla2x00_alloc_iocbs()1600 cnt = RD_REG_DWORD(®->isp24.req_q_out); in qla2x00_alloc_iocbs()1647 RD_REG_DWORD(&ioreg->hccr); in qla2x00_start_iocbs()
737 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); in qla24xx_pci_config()991 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()1011 d2 = RD_REG_DWORD(®->ctrl_status); in qla24xx_reset_risc()1014 d2 = RD_REG_DWORD(®->ctrl_status); in qla24xx_reset_risc()1036 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()1039 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()1042 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()1778 RD_REG_DWORD(&ioreg->hccr); in qla24xx_config_rings()4319 RD_REG_DWORD(®->hccr); in qla24xx_reset_adapter()4321 RD_REG_DWORD(®->hccr); in qla24xx_reset_adapter()
1424 RD_REG_DWORD(®->ictrl); in qla24xx_enable_intrs()1439 RD_REG_DWORD(®->ictrl); in qla24xx_disable_intrs()3847 stat = RD_REG_DWORD(®->hccr); in qla2xxx_pci_mmio_enabled()3851 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()3855 stat = RD_REG_DWORD(®24->host_status); in qla2xxx_pci_mmio_enabled()
154 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()180 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()259 ictrl = RD_REG_DWORD(®->isp24.ictrl); in qla2x00_mailbox_command()3979 stat = RD_REG_DWORD(®->host_status); in qla81xx_write_mpi_register()3990 RD_REG_DWORD(®->hccr); in qla81xx_write_mpi_register()
108 #define RD_REG_DWORD(addr) readl(addr) macro