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Searched refs:RADEON_WRITE (Results 1 – 6 of 6) sorted by relevance

/linux-2.6.39/drivers/gpu/drm/radeon/
Dr600_cp.c233 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_flush_gart_range()
234 …RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_si… in r600_vm_flush_gart_range()
235 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); in r600_vm_flush_gart_range()
252 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
253 …RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); in r600_vm_init()
261 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); in r600_vm_init()
262 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); in r600_vm_init()
264 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); in r600_vm_init()
265 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); in r600_vm_init()
[all …]
Dradeon_cp.c136 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); in R500_READ_MCIND()
138 RADEON_WRITE(R520_MC_IND_INDEX, 0); in R500_READ_MCIND()
145 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); in RS480_READ_MCIND()
147 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); in RS480_READ_MCIND()
154 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); in RS690_READ_MCIND()
156 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); in RS690_READ_MCIND()
163 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | in RS600_READ_MCIND()
203 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); in radeon_write_fb_location()
205 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); in radeon_write_fb_location()
216 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); in radeon_write_fb_location()
[all …]
Dradeon_irq.c48 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_irq_set_state()
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in r500_vbl_irq_set_state()
149 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK); in radeon_acknowledge_irqs()
151 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK); in radeon_acknowledge_irqs()
160 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs); in radeon_acknowledge_irqs()
343 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); in radeon_driver_irq_preinstall()
344 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); in radeon_driver_irq_preinstall()
379 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); in radeon_driver_irq_uninstall()
381 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); in radeon_driver_irq_uninstall()
Dradeon_drv.h1852 #define RADEON_WRITE(reg, val) \ macro
1868 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1875 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1880 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1881 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1882 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1887 RADEON_WRITE(RS480_NB_MC_INDEX, \
1889 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1890 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1895 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
[all …]
Dradeon_drv.c174 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); in radeon_suspend()
175 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); in radeon_suspend()
188 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in radeon_resume()
189 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_resume()
Dradeon_state.c1967 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index, in radeon_apply_surface_regs()
1969 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index, in radeon_apply_surface_regs()
1971 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index, in radeon_apply_surface_regs()