Searched refs:RADEON_VCLK_ECP_CNTL (Results 1 – 4 of 4) sorted by relevance
516 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()519 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()569 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()572 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()722 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()726 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()758 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()762 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()809 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating()813 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()[all …]
909 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()981 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()
621 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()629 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect()669 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()
1778 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ macro