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/linux-2.6.39/arch/blackfin/lib/
Dudivsi3.S28 R3 = R1 >> 15; /* and Y is a 15-bit number */ define
29 R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
83 R3 += -1; /* if so, Y is 0x00008nnn */
89 R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */ define
92 R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
122 R3 = 1; define
131 IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
134 R3 = -R1; define
135 [--SP] = R3;
145 R3 = 0; /* Clear partial remainder */ define
[all …]
Dmemcpy.S42 R3 = R1 + R2; define
43 CC = R0 < R3; /* and dst < src+len */
49 R3 = R1 | R0; define
51 R3 = R3 & R1; define
52 CC = R3; /* low bits set on either address? */
64 R3 = B[P1++] (X); define
66 B[P0++] = R3;
75 R3 = [I1++]; define
78 [P0++] = R3;
80 R3 = [I1++]; define
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Dmemmove.S29 R3 = R1 + R2; define
30 CC = R0 <= R3 (IU); /* (From+len) >= To */
33 R3 = 11; define
34 CC = R2 <= R3;
36 R3 = R1 | R0; /* OR addresses together */ define
37 R3 <<= 30; /* check bottom two bits */
44 R3 = 3; define
45 R2 = R2 & R3; /* remainder */
Dmuldi3.S51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
55 A0 = R0.l * R3.l (FU); /* E2 */
59 R3 = A1.w; define
69 R0 = PACK (R0.l, R3.l);
Dmemset.S29 R3 = R0 + R2; /* end */ define
43 P2 = R3;
54 R2 = R3; /* end point */
55 R3 = P0; /* current position */ define
56 R2 = R2 - R3; /* bytes left */
Dsmulsi3_highpart.S19 R3 = R1.H * R0.L (IS,M); define
26 R1.L = R1.L + R3.L;
29 R3 >>>= 16;
30 R1 = R1 + R3;
Dmemchr.S32 R3 = B[P0++](Z); define
33 CC = R3 == R1;
Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
23 R0 = R0 + R3;
Dstrncpy.S56 R3 = 0x20; define
57 CC = R2 < R3;
Dmemcmp.S35 R3 = 3; define
36 R2 = R2 & R3; /* remainder */
Dins.S24 # define DO_CLI cli R3;
35 # define DO_STI 2: sti R3;
Ddivsi3.S39 R3 = R0 ^ R1; define
163 CC = bittst(R3,30);
191 CC = bittst(R3,30);
/linux-2.6.39/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S56 #define R3 %rdx macro
232 movq (R3), R1
233 movq 8(R3), R3
235 input_whitening(R3,%r11,c_offset)
240 shr $32, R3
243 encrypt_round(R0,R1,R2,R3,0);
244 encrypt_round(R2,R3,R0,R1,8);
245 encrypt_round(R0,R1,R2,R3,2*8);
246 encrypt_round(R2,R3,R0,R1,3*8);
247 encrypt_round(R0,R1,R2,R3,4*8);
[all …]
Dtwofish-i586-asm_32.S247 encrypt_round(R0,R1,R2,R3,0);
248 encrypt_round(R2,R3,R0,R1,8);
249 encrypt_round(R0,R1,R2,R3,2*8);
250 encrypt_round(R2,R3,R0,R1,3*8);
251 encrypt_round(R0,R1,R2,R3,4*8);
252 encrypt_round(R2,R3,R0,R1,5*8);
253 encrypt_round(R0,R1,R2,R3,6*8);
254 encrypt_round(R2,R3,R0,R1,7*8);
255 encrypt_round(R0,R1,R2,R3,8*8);
256 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
Daes-x86_64-asm_64.S30 #define R3 %rcx macro
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
136 #define return epilogue(R8,R2,R9,R7,R5,R6,R3,R4,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4) \
150 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4)
/linux-2.6.39/drivers/net/wan/
Dz85230.c468 write_zsreg(chan, R3, chan->regs[3] | RxENABLE); in z8530_status()
473 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); in z8530_status()
589 write_zsreg(chan, R3, chan->regs[3] | RxENABLE); in z8530_dma_status()
594 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); in z8530_dma_status()
725 intr = read_zsreg(&dev->chanA, R3); in z8530_interrupt()
807 write_zsreg(c, R3, c->regs[R3]|RxENABLE); in z8530_sync_open()
836 write_zsreg(c, R3, c->regs[R3]); in z8530_sync_close()
960 write_zsreg(c, R3, c->regs[R3]|RxENABLE); in z8530_sync_dma_open()
1029 write_zsreg(c, R3, c->regs[R3]); in z8530_sync_dma_close()
1133 write_zsreg(c, R3, c->regs[R3]|RxENABLE); in z8530_sync_txdma_open()
[all …]
/linux-2.6.39/drivers/staging/rt2860/common/
Dcmm_asic.c636 unsigned long R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0; in AsicSwitchChannel() local
767 R3 = (RFRegTable[index]. in AsicSwitchChannel()
768 R3 & 0xffffc1ff); in AsicSwitchChannel()
782 R3 |= (TxPwer << 10); in AsicSwitchChannel()
791 R3 |= in AsicSwitchChannel()
820 R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); /* set TX power0 */ in AsicSwitchChannel()
835 pAd->LatchRfRegs.R3 = R3; in AsicSwitchChannel()
845 R3 & (~0x04))); in AsicSwitchChannel()
858 R3 | 0x04)); in AsicSwitchChannel()
871 R3 & (~0x04))); in AsicSwitchChannel()
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/linux-2.6.39/arch/parisc/kernel/
Dunaligned.c120 #define R3(i) ((i)&0x1f) macro
543 ret = emulate_ldh(regs, R3(regs->iir)); in handle_unaligned()
550 ret = emulate_ldw(regs, R3(regs->iir),0); in handle_unaligned()
567 ret = emulate_ldd(regs, R3(regs->iir),0); in handle_unaligned()
587 ret = emulate_ldd(regs,R3(regs->iir),1); in handle_unaligned()
601 ret = emulate_std(regs,R3(regs->iir),1); in handle_unaligned()
/linux-2.6.39/drivers/tty/serial/
Dsunzilog.c208 write_zsreg(channel, R3, regs[R3] & ~RxENAB); in __load_zsregs()
255 write_zsreg(channel, R3, regs[R3]); in __load_zsregs()
545 r3 = read_zsreg(channel, R3); in sunzilog_interrupt()
792 up->curregs[R3] |= RxENAB; in __sunzilog_startup()
852 up->curregs[R3] &= ~RxENAB; in sunzilog_shutdown()
882 up->curregs[R3] &= ~RxN_MASK; in sunzilog_convert_to_zs()
886 up->curregs[R3] |= Rx5; in sunzilog_convert_to_zs()
891 up->curregs[R3] |= Rx6; in sunzilog_convert_to_zs()
896 up->curregs[R3] |= Rx7; in sunzilog_convert_to_zs()
902 up->curregs[R3] |= Rx8; in sunzilog_convert_to_zs()
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Dip22zilog.c190 write_zsreg(channel, R3, regs[R3] & ~RxENAB); in __load_zsregs()
223 write_zsreg(channel, R3, regs[R3]); in __load_zsregs()
445 r3 = read_zsreg(channel, R3); in ip22zilog_interrupt()
727 up->curregs[R3] |= RxENAB; in __ip22zilog_startup()
787 up->curregs[R3] &= ~RxENAB; in ip22zilog_shutdown()
1140 up->curregs[R3] = RxENAB | Rx8; in ip22zilog_prepare()
Dpmac_zilog.c159 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); in pmz_load_zsregs()
191 write_zsreg(uap, R3, regs[R3]); in pmz_load_zsregs()
478 r3 = read_zsreg(uap_a, R3); in pmz_interrupt()
904 uap->curregs[R3] = Rx8; in __pmz_startup()
921 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); in __pmz_startup()
1044 uap->curregs[R3] &= ~RxENABLE; in pmz_shutdown()
1677 uap->curregs[R3] &= ~RxENABLE; in pmz_suspend()
Dzs.h62 #define R3 3 macro
/linux-2.6.39/drivers/staging/rt2860/
Drtmp_type.h75 unsigned long R3; member
/linux-2.6.39/drivers/net/hamradio/
Dscc.c360 or(scc,R3,ENT_HM|RxENABLE); /* enable the receiver, hunt mode */ in start_hunt()
473 cl(scc,R3,ENT_HM|RxENABLE); /* disable the receiver */ in scc_exint()
525 or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ in scc_rxint()
539 or(scc, R3, ENT_HM); in scc_rxint()
555 or(scc, R3, ENT_HM); in scc_rxint()
579 or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ in scc_spint()
676 for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++) in scc_isr()
802 wr(scc,R3,Rx8|RxCRC_ENAB); /* RX 8 bits/char, CRC, disabled */ in init_channel()
924 cl(scc, R3, RxENABLE|ENT_HM); /* switch off receiver */ in scc_key_trx()
962 cl(scc, R3, RxENABLE); in scc_key_trx()
[all …]
Dz8530.h9 #define R3 3 macro

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