Searched refs:PORT_PREF0 (Results 1 – 9 of 9) sorted by relevance
51 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)57 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)65 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)87 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)94 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)102 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)123 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)130 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)138 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
49 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)55 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)63 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
53 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)59 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)67 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
56 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)62 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)70 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
72 (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); in bfin_dcache_init()
557 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ macro