Searched refs:PMU1_PLL0_PC2_M5DIV_MASK (Results 1 – 2 of 2) sorted by relevance
930 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff macro
2670 pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK); in si_pmu_set_4330_plldivs()