Searched refs:PLL_BASE (Results 1 – 1 of 1) sorted by relevance
81 #define PLL_BASE 0x0 macro631 u32 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_init()657 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_enable()660 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_enable()691 val = clk_readl(c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()706 clk_writel(val, c->reg + PLL_BASE); in tegra2_pll_clk_set_rate()754 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()758 val = clk_readl(c->reg + PLL_BASE); in tegra2_plle_clk_enable()760 clk_writel(val, c->reg + PLL_BASE); in tegra2_plle_clk_enable()2334 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); in tegra_clk_suspend()[all …]