1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _h_pcicfg_ 18 #define _h_pcicfg_ 19 20 /* The following inside ifndef's so we don't collide with NTDDK.H */ 21 #ifndef PCI_MAX_BUS 22 #define PCI_MAX_BUS 0x100 23 #endif 24 #ifndef PCI_MAX_DEVICES 25 #define PCI_MAX_DEVICES 0x20 26 #endif 27 #ifndef PCI_MAX_FUNCTION 28 #define PCI_MAX_FUNCTION 0x8 29 #endif 30 31 #ifndef PCI_INVALID_VENDORID 32 #define PCI_INVALID_VENDORID 0xffff 33 #endif 34 #ifndef PCI_INVALID_DEVICEID 35 #define PCI_INVALID_DEVICEID 0xffff 36 #endif 37 38 /* Convert between bus-slot-function-register and config addresses */ 39 40 #define PCICFG_BUS_SHIFT 16 /* Bus shift */ 41 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */ 42 #define PCICFG_FUN_SHIFT 8 /* Function shift */ 43 #define PCICFG_OFF_SHIFT 0 /* Register shift */ 44 45 #define PCICFG_BUS_MASK 0xff /* Bus mask */ 46 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */ 47 #define PCICFG_FUN_MASK 7 /* Function mask */ 48 #define PCICFG_OFF_MASK 0xff /* Bus mask */ 49 50 #define PCI_CONFIG_ADDR(b, s, f, o) \ 51 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \ 52 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \ 53 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \ 54 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT)) 55 56 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK) 57 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK) 58 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK) 59 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK) 60 61 /* PCIE Config space accessing MACROS */ 62 63 #define PCIECFG_BUS_SHIFT 24 /* Bus shift */ 64 #define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */ 65 #define PCIECFG_FUN_SHIFT 16 /* Function shift */ 66 #define PCIECFG_OFF_SHIFT 0 /* Register shift */ 67 68 #define PCIECFG_BUS_MASK 0xff /* Bus mask */ 69 #define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */ 70 #define PCIECFG_FUN_MASK 7 /* Function mask */ 71 #define PCIECFG_OFF_MASK 0xfff /* Register mask */ 72 73 #define PCIE_CONFIG_ADDR(b, s, f, o) \ 74 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \ 75 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \ 76 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \ 77 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT)) 78 79 #define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK) 80 #define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK) 81 #define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK) 82 #define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK) 83 84 /* The actual config space */ 85 86 #define PCI_BAR_MAX 6 87 88 #define PCI_ROM_BAR 8 89 90 #define PCR_RSVDA_MAX 2 91 92 /* Bits in PCI bars' flags */ 93 94 #define PCIBAR_FLAGS 0xf 95 #define PCIBAR_IO 0x1 96 #define PCIBAR_MEM1M 0x2 97 #define PCIBAR_MEM64 0x4 98 #define PCIBAR_PREFETCH 0x8 99 #define PCIBAR_MEM32_MASK 0xFFFFFF80 100 101 /* pci config status reg has a bit to indicate that capability ptr is present */ 102 103 #define PCI_CAPPTR_PRESENT 0x0010 104 105 typedef struct _pci_config_regs { 106 u16 vendor; 107 u16 device; 108 u16 command; 109 u16 status; 110 u8 rev_id; 111 u8 prog_if; 112 u8 sub_class; 113 u8 base_class; 114 u8 cache_line_size; 115 u8 latency_timer; 116 u8 header_type; 117 u8 bist; 118 u32 base[PCI_BAR_MAX]; 119 u32 cardbus_cis; 120 u16 subsys_vendor; 121 u16 subsys_id; 122 u32 baserom; 123 u32 rsvd_a[PCR_RSVDA_MAX]; 124 u8 int_line; 125 u8 int_pin; 126 u8 min_gnt; 127 u8 max_lat; 128 u8 dev_dep[192]; 129 } pci_config_regs; 130 131 #define SZPCR (sizeof (pci_config_regs)) 132 #define MINSZPCR 64 /* offsetof (dev_dep[0] */ 133 134 /* A structure for the config registers is nice, but in most 135 * systems the config space is not memory mapped, so we need 136 * field offsetts. :-( 137 */ 138 #define PCI_CFG_VID 0 139 #define PCI_CFG_DID 2 140 #define PCI_CFG_CMD 4 141 #define PCI_CFG_STAT 6 142 #define PCI_CFG_REV 8 143 #define PCI_CFG_PROGIF 9 144 #define PCI_CFG_SUBCL 0xa 145 #define PCI_CFG_BASECL 0xb 146 #define PCI_CFG_CLSZ 0xc 147 #define PCI_CFG_LATTIM 0xd 148 #define PCI_CFG_HDR 0xe 149 #define PCI_CFG_BIST 0xf 150 #define PCI_CFG_BAR0 0x10 151 #define PCI_CFG_BAR1 0x14 152 #define PCI_CFG_BAR2 0x18 153 #define PCI_CFG_BAR3 0x1c 154 #define PCI_CFG_BAR4 0x20 155 #define PCI_CFG_BAR5 0x24 156 #define PCI_CFG_CIS 0x28 157 #define PCI_CFG_SVID 0x2c 158 #define PCI_CFG_SSID 0x2e 159 #define PCI_CFG_ROMBAR 0x30 160 #define PCI_CFG_CAPPTR 0x34 161 #define PCI_CFG_INT 0x3c 162 #define PCI_CFG_PIN 0x3d 163 #define PCI_CFG_MINGNT 0x3e 164 #define PCI_CFG_MAXLAT 0x3f 165 166 /* Classes and subclasses */ 167 168 typedef enum { 169 PCI_CLASS_OLD = 0, 170 PCI_CLASS_DASDI, 171 PCI_CLASS_NET, 172 PCI_CLASS_DISPLAY, 173 PCI_CLASS_MMEDIA, 174 PCI_CLASS_MEMORY, 175 PCI_CLASS_BRIDGE, 176 PCI_CLASS_COMM, 177 PCI_CLASS_BASE, 178 PCI_CLASS_INPUT, 179 PCI_CLASS_DOCK, 180 PCI_CLASS_CPU, 181 PCI_CLASS_SERIAL, 182 PCI_CLASS_INTELLIGENT = 0xe, 183 PCI_CLASS_SATELLITE, 184 PCI_CLASS_CRYPT, 185 PCI_CLASS_DSP, 186 PCI_CLASS_XOR = 0xfe 187 } pci_classes; 188 189 typedef enum { 190 PCI_DASDI_SCSI, 191 PCI_DASDI_IDE, 192 PCI_DASDI_FLOPPY, 193 PCI_DASDI_IPI, 194 PCI_DASDI_RAID, 195 PCI_DASDI_OTHER = 0x80 196 } pci_dasdi_subclasses; 197 198 typedef enum { 199 PCI_NET_ETHER, 200 PCI_NET_TOKEN, 201 PCI_NET_FDDI, 202 PCI_NET_ATM, 203 PCI_NET_OTHER = 0x80 204 } pci_net_subclasses; 205 206 typedef enum { 207 PCI_DISPLAY_VGA, 208 PCI_DISPLAY_XGA, 209 PCI_DISPLAY_3D, 210 PCI_DISPLAY_OTHER = 0x80 211 } pci_display_subclasses; 212 213 typedef enum { 214 PCI_MMEDIA_VIDEO, 215 PCI_MMEDIA_AUDIO, 216 PCI_MMEDIA_PHONE, 217 PCI_MEDIA_OTHER = 0x80 218 } pci_mmedia_subclasses; 219 220 typedef enum { 221 PCI_MEMORY_RAM, 222 PCI_MEMORY_FLASH, 223 PCI_MEMORY_OTHER = 0x80 224 } pci_memory_subclasses; 225 226 typedef enum { 227 PCI_BRIDGE_HOST, 228 PCI_BRIDGE_ISA, 229 PCI_BRIDGE_EISA, 230 PCI_BRIDGE_MC, 231 PCI_BRIDGE_PCI, 232 PCI_BRIDGE_PCMCIA, 233 PCI_BRIDGE_NUBUS, 234 PCI_BRIDGE_CARDBUS, 235 PCI_BRIDGE_RACEWAY, 236 PCI_BRIDGE_OTHER = 0x80 237 } pci_bridge_subclasses; 238 239 typedef enum { 240 PCI_COMM_UART, 241 PCI_COMM_PARALLEL, 242 PCI_COMM_MULTIUART, 243 PCI_COMM_MODEM, 244 PCI_COMM_OTHER = 0x80 245 } pci_comm_subclasses; 246 247 typedef enum { 248 PCI_BASE_PIC, 249 PCI_BASE_DMA, 250 PCI_BASE_TIMER, 251 PCI_BASE_RTC, 252 PCI_BASE_PCI_HOTPLUG, 253 PCI_BASE_OTHER = 0x80 254 } pci_base_subclasses; 255 256 typedef enum { 257 PCI_INPUT_KBD, 258 PCI_INPUT_PEN, 259 PCI_INPUT_MOUSE, 260 PCI_INPUT_SCANNER, 261 PCI_INPUT_GAMEPORT, 262 PCI_INPUT_OTHER = 0x80 263 } pci_input_subclasses; 264 265 typedef enum { 266 PCI_DOCK_GENERIC, 267 PCI_DOCK_OTHER = 0x80 268 } pci_dock_subclasses; 269 270 typedef enum { 271 PCI_CPU_386, 272 PCI_CPU_486, 273 PCI_CPU_PENTIUM, 274 PCI_CPU_ALPHA = 0x10, 275 PCI_CPU_POWERPC = 0x20, 276 PCI_CPU_MIPS = 0x30, 277 PCI_CPU_COPROC = 0x40, 278 PCI_CPU_OTHER = 0x80 279 } pci_cpu_subclasses; 280 281 typedef enum { 282 PCI_SERIAL_IEEE1394, 283 PCI_SERIAL_ACCESS, 284 PCI_SERIAL_SSA, 285 PCI_SERIAL_USB, 286 PCI_SERIAL_FIBER, 287 PCI_SERIAL_SMBUS, 288 PCI_SERIAL_OTHER = 0x80 289 } pci_serial_subclasses; 290 291 typedef enum { 292 PCI_INTELLIGENT_I2O 293 } pci_intelligent_subclasses; 294 295 typedef enum { 296 PCI_SATELLITE_TV, 297 PCI_SATELLITE_AUDIO, 298 PCI_SATELLITE_VOICE, 299 PCI_SATELLITE_DATA, 300 PCI_SATELLITE_OTHER = 0x80 301 } pci_satellite_subclasses; 302 303 typedef enum { 304 PCI_CRYPT_NETWORK, 305 PCI_CRYPT_ENTERTAINMENT, 306 PCI_CRYPT_OTHER = 0x80 307 } pci_crypt_subclasses; 308 309 typedef enum { 310 PCI_DSP_DPIO, 311 PCI_DSP_OTHER = 0x80 312 } pci_dsp_subclasses; 313 314 typedef enum { 315 PCI_XOR_QDMA, 316 PCI_XOR_OTHER = 0x80 317 } pci_xor_subclasses; 318 319 /* Header types */ 320 #define PCI_HEADER_MULTI 0x80 321 #define PCI_HEADER_MASK 0x7f 322 typedef enum { 323 PCI_HEADER_NORMAL, 324 PCI_HEADER_BRIDGE, 325 PCI_HEADER_CARDBUS 326 } pci_header_types; 327 328 /* Overlay for a PCI-to-PCI bridge */ 329 330 #define PPB_RSVDA_MAX 2 331 #define PPB_RSVDD_MAX 8 332 333 typedef struct _ppb_config_regs { 334 u16 vendor; 335 u16 device; 336 u16 command; 337 u16 status; 338 u8 rev_id; 339 u8 prog_if; 340 u8 sub_class; 341 u8 base_class; 342 u8 cache_line_size; 343 u8 latency_timer; 344 u8 header_type; 345 u8 bist; 346 u32 rsvd_a[PPB_RSVDA_MAX]; 347 u8 prim_bus; 348 u8 sec_bus; 349 u8 sub_bus; 350 u8 sec_lat; 351 u8 io_base; 352 u8 io_lim; 353 u16 sec_status; 354 u16 mem_base; 355 u16 mem_lim; 356 u16 pf_mem_base; 357 u16 pf_mem_lim; 358 u32 pf_mem_base_hi; 359 u32 pf_mem_lim_hi; 360 u16 io_base_hi; 361 u16 io_lim_hi; 362 u16 subsys_vendor; 363 u16 subsys_id; 364 u32 rsvd_b; 365 u8 rsvd_c; 366 u8 int_pin; 367 u16 bridge_ctrl; 368 u8 chip_ctrl; 369 u8 diag_ctrl; 370 u16 arb_ctrl; 371 u32 rsvd_d[PPB_RSVDD_MAX]; 372 u8 dev_dep[192]; 373 } ppb_config_regs; 374 375 /* PCI CAPABILITY DEFINES */ 376 #define PCI_CAP_POWERMGMTCAP_ID 0x01 377 #define PCI_CAP_MSICAP_ID 0x05 378 #define PCI_CAP_VENDSPEC_ID 0x09 379 #define PCI_CAP_PCIECAP_ID 0x10 380 381 /* Data structure to define the Message Signalled Interrupt facility 382 * Valid for PCI and PCIE configurations 383 */ 384 typedef struct _pciconfig_cap_msi { 385 u8 capID; 386 u8 nextptr; 387 u16 msgctrl; 388 u32 msgaddr; 389 } pciconfig_cap_msi; 390 391 /* Data structure to define the Power management facility 392 * Valid for PCI and PCIE configurations 393 */ 394 typedef struct _pciconfig_cap_pwrmgmt { 395 u8 capID; 396 u8 nextptr; 397 u16 pme_cap; 398 u16 pme_sts_ctrl; 399 u8 pme_bridge_ext; 400 u8 data; 401 } pciconfig_cap_pwrmgmt; 402 403 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ 404 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 405 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 406 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 407 408 /* Data structure to define the PCIE capability */ 409 typedef struct _pciconfig_cap_pcie { 410 u8 capID; 411 u8 nextptr; 412 u16 pcie_cap; 413 u32 dev_cap; 414 u16 dev_ctrl; 415 u16 dev_status; 416 u32 link_cap; 417 u16 link_ctrl; 418 u16 link_status; 419 u32 slot_cap; 420 u16 slot_ctrl; 421 u16 slot_status; 422 u16 root_ctrl; 423 u16 root_cap; 424 u32 root_status; 425 } pciconfig_cap_pcie; 426 427 /* PCIE Enhanced CAPABILITY DEFINES */ 428 #define PCIE_EXTCFG_OFFSET 0x100 429 #define PCIE_ADVERRREP_CAPID 0x0001 430 #define PCIE_VC_CAPID 0x0002 431 #define PCIE_DEVSNUM_CAPID 0x0003 432 #define PCIE_PWRBUDGET_CAPID 0x0004 433 434 /* PCIE Extended configuration */ 435 #define PCIE_ADV_CORR_ERR_MASK 0x114 436 #define CORR_ERR_RE (1 << 0) /* Receiver */ 437 #define CORR_ERR_BT (1 << 6) /* Bad TLP */ 438 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */ 439 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */ 440 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */ 441 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \ 442 CORR_ERR_RR | CORR_ERR_RT) 443 444 /* PCIE Root Control Register bits (Host mode only) */ 445 #define PCIE_RC_CORR_SERR_EN 0x0001 446 #define PCIE_RC_NONFATAL_SERR_EN 0x0002 447 #define PCIE_RC_FATAL_SERR_EN 0x0004 448 #define PCIE_RC_PME_INT_EN 0x0008 449 #define PCIE_RC_CRS_EN 0x0010 450 451 /* PCIE Root Capability Register bits (Host mode only) */ 452 #define PCIE_RC_CRS_VISIBILITY 0x0001 453 454 /* Header to define the PCIE specific capabilities in the extended config space */ 455 typedef struct _pcie_enhanced_caphdr { 456 u16 capID; 457 u16 cap_ver:4; 458 u16 next_ptr:12; 459 } pcie_enhanced_caphdr; 460 461 /* Everything below is BRCM HND proprietary */ 462 463 /* Brcm PCI configuration registers */ 464 #define cap_list rsvd_a[0] 465 #define bar0_window dev_dep[0x80 - 0x40] 466 #define bar1_window dev_dep[0x84 - 0x40] 467 #define sprom_control dev_dep[0x88 - 0x40] 468 #define PCI_BAR0_WIN 0x80 /* backplane address space accessed by BAR0 */ 469 #define PCI_BAR1_WIN 0x84 /* backplane address space accessed by BAR1 */ 470 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 471 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 472 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 473 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 474 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 475 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 476 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 477 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */ 478 #define PCI_BAR0_WIN2 0xac /* backplane address space accessed by second 4KB of BAR0 */ 479 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 480 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 481 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 482 483 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 484 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 485 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 486 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 487 * 8KB window, so their address is the "regular" 488 * address plus 4K 489 */ 490 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 491 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 492 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 493 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 494 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 495 496 /* On AI chips we have a second window to map DMP regs are mapped: */ 497 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */ 498 499 /* PCI_INT_STATUS */ 500 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 501 502 /* PCI_INT_MASK */ 503 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 504 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 505 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 506 507 /* PCI_SPROM_CONTROL */ 508 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 509 #define SPROM_LOCKED 0x08 /* SPROM Locked */ 510 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 511 #define SPROM_WRITEEN 0x10 /* SPROM write enable */ 512 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 513 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */ 514 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 515 516 /* Bits in PCI command and status regs */ 517 #define PCI_CMD_IO 0x00000001 /* I/O enable */ 518 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */ 519 #define PCI_CMD_MASTER 0x00000004 /* Master enable */ 520 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */ 521 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */ 522 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */ 523 #define PCI_STAT_TA 0x08000000 /* target abort status */ 524 #endif /* _h_pcicfg_ */ 525