Searched refs:PCI_BAR0_WIN2 (Results 1 – 2 of 2) sorted by relevance
478 #define PCI_BAR0_WIN2 0xac /* backplane address space accessed by second 4KB of BAR0 */ macro
352 pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap); in ai_setcoreidx()