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Searched refs:NVWriteVgaCrtc (Results 1 – 9 of 9) sorted by relevance

/linux-2.6.39/drivers/gpu/drm/nouveau/
Dnouveau_hw.h183 static inline void NVWriteVgaCrtc(struct drm_device *dev, in NVWriteVgaCrtc() function
220 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVWriteVgaCrtc5758()
221 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value); in NVWriteVgaCrtc5758()
226 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); in NVReadVgaCrtc5758()
347 NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11); in nv_lock_vga_crtc_base()
371 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21); in nv_lock_vga_crtc_shadow()
383 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX, in NVLockVgaCrtcs()
387 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX, in NVLockVgaCrtcs()
432 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX, in nv_set_crtc_base()
448 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); in nv_show_cursor()
Dnv04_dac.c139 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80); in nv04_dac_detect()
151 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, in nv04_dac_detect()
154 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); in nv04_dac_detect()
206 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); in nv04_dac_detect()
207 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); in nv04_dac_detect()
209 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode); in nv04_dac_detect()
Dnv04_tv.c87 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv04_tv_dpms()
107 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX, in nv04_tv_bind()
109 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49, in nv04_tv_bind()
Dnv04_cursor.c33 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
Dnouveau_i2c.c38 NVWriteVgaCrtc(dev, 0, i2c->wr, val | 0x01); in nv04_i2c_setscl()
49 NVWriteVgaCrtc(dev, 0, i2c->wr, val | 0x01); in nv04_i2c_setsda()
Dnv04_crtc.c45 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
211 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); in nv_crtc_dpms()
214 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); in nv_crtc_dpms()
703 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); in nv_crtc_commit()
Dnouveau_hw.c99 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); in NVSetOwner()
102 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
645 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
Dnv04_dfp.c271 NVWriteVgaCrtc(dev, head ^ 1, in nv04_dfp_prepare()
Dnouveau_bios.c491 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); in bios_idxprt_wr()