1 /****************************************************************************/ 2 3 /* 4 * m5249sim.h -- ColdFire 5249 System Integration Module support. 5 * 6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) 7 */ 8 9 /****************************************************************************/ 10 #ifndef m5249sim_h 11 #define m5249sim_h 12 /****************************************************************************/ 13 14 #define CPU_NAME "COLDFIRE(m5249)" 15 #define CPU_INSTR_PER_JIFFY 3 16 #define MCF_BUSCLK (MCF_CLK / 2) 17 18 #include <asm/m52xxacr.h> 19 20 /* 21 * The 5249 has a second MBAR region, define its address. 22 */ 23 #define MCF_MBAR2 0x80000000 24 25 /* 26 * Define the 5249 SIM register set addresses. 27 */ 28 #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ 29 #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ 30 #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 31 #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 32 #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ 33 #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ 34 #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 35 #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ 36 #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ 37 #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ 38 #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 39 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 40 #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 41 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 42 #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 43 #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 44 #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 45 #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 46 #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 47 #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 48 #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 49 #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 50 51 #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 52 #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 53 #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 54 #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 55 #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 56 #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 57 #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 58 #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 59 #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 60 #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 61 #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 62 #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 63 64 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 65 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 66 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 67 #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ 68 #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ 69 70 /* 71 * Timer module. 72 */ 73 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 74 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 75 76 /* 77 * UART module. 78 */ 79 #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 80 #define MCFUART_BASE2 0x200 /* Base address of UART2 */ 81 82 /* 83 * DMA unit base addresses. 84 */ 85 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 86 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 87 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 88 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 89 90 /* 91 * Some symbol defines for the above... 92 */ 93 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 94 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 95 #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 96 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 97 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 98 #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 99 #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 100 #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 101 #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 102 #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ 103 104 /* 105 * Define system peripheral IRQ usage. 106 */ 107 #define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ 108 #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 109 #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 110 111 /* 112 * General purpose IO registers (in MBAR2). 113 */ 114 #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ 115 #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ 116 #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ 117 #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ 118 #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ 119 #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ 120 #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ 121 #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ 122 123 #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ 124 #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ 125 #define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ 126 127 #define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ 128 #define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ 129 #define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ 130 #define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ 131 #define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ 132 #define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ 133 #define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ 134 #define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ 135 136 #define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ 137 138 #define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ 139 #define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ 140 141 /* 142 * Define the base interrupt for the second interrupt controller. 143 * We set it to 128, out of the way of the base interrupts, and plenty 144 * of room for its 64 interrupts. 145 */ 146 #define MCFINTC2_VECBASE 128 147 148 #define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32) 149 #define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33) 150 #define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34) 151 #define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35) 152 #define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36) 153 #define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37) 154 #define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38) 155 #define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39) 156 157 /* 158 * Generic GPIO support 159 */ 160 #define MCFGPIO_PIN_MAX 64 161 #define MCFGPIO_IRQ_MAX -1 162 #define MCFGPIO_IRQ_VECBASE -1 163 164 /****************************************************************************/ 165 166 #ifdef __ASSEMBLER__ 167 168 /* 169 * The M5249C3 board needs a little help getting all its SIM devices 170 * initialized at kernel start time. dBUG doesn't set much up, so 171 * we need to do it manually. 172 */ 173 .macro m5249c3_setup 174 /* 175 * Set MBAR1 and MBAR2, just incase they are not set. 176 */ 177 movel #0x10000001,%a0 178 movec %a0,%MBAR /* map MBAR region */ 179 subql #1,%a0 /* get MBAR address in a0 */ 180 181 movel #0x80000001,%a1 182 movec %a1,#3086 /* map MBAR2 region */ 183 subql #1,%a1 /* get MBAR2 address in a1 */ 184 185 /* 186 * Move secondary interrupts to their base (128). 187 */ 188 moveb #MCFINTC2_VECBASE,%d0 189 moveb %d0,0x16b(%a1) /* interrupt base register */ 190 191 /* 192 * Work around broken CSMR0/DRAM vector problem. 193 */ 194 movel #0x001F0021,%d0 /* disable C/I bit */ 195 movel %d0,0x84(%a0) /* set CSMR0 */ 196 197 /* 198 * Disable the PLL firstly. (Who knows what state it is 199 * in here!). 200 */ 201 movel 0x180(%a1),%d0 /* get current PLL value */ 202 andl #0xfffffffe,%d0 /* PLL bypass first */ 203 movel %d0,0x180(%a1) /* set PLL register */ 204 nop 205 206 #if CONFIG_CLOCK_FREQ == 140000000 207 /* 208 * Set initial clock frequency. This assumes M5249C3 board 209 * is fitted with 11.2896MHz crystal. It will program the 210 * PLL for 140MHz. Lets go fast :-) 211 */ 212 movel #0x125a40f0,%d0 /* set for 140MHz */ 213 movel %d0,0x180(%a1) /* set PLL register */ 214 orl #0x1,%d0 215 movel %d0,0x180(%a1) /* set PLL register */ 216 #endif 217 218 /* 219 * Setup CS1 for ethernet controller. 220 * (Setup as per M5249C3 doco). 221 */ 222 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ 223 movel %d0,0x8c(%a0) 224 movel #0x001f0021,%d0 /* CS1 size of 1Mb */ 225 movel %d0,0x90(%a0) 226 movew #0x0080,%d0 /* CS1 = 16bit port, AA */ 227 movew %d0,0x96(%a0) 228 229 /* 230 * Setup CS2 for IDE interface. 231 */ 232 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ 233 movel %d0,0x98(%a0) 234 movel #0x001f0001,%d0 /* CS2 size of 1MB */ 235 movel %d0,0x9c(%a0) 236 movew #0x0080,%d0 /* CS2 = 16bit, TA */ 237 movew %d0,0xa2(%a0) 238 239 movel #0x00107000,%d0 /* IDEconfig1 */ 240 movel %d0,0x18c(%a1) 241 movel #0x000c0400,%d0 /* IDEconfig2 */ 242 movel %d0,0x190(%a1) 243 244 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ 245 orl %d0,0xc(%a1) /* function GPIO19 */ 246 orl %d0,0x8(%a1) /* enable GPIO19 as output */ 247 orl %d0,0x4(%a1) /* de-assert IDE reset */ 248 .endm 249 250 #define PLATFORM_SETUP m5249c3_setup 251 252 #endif /* __ASSEMBLER__ */ 253 254 /****************************************************************************/ 255 #endif /* m5249sim_h */ 256