1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_le32(name, ptr) \ 45 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get(name, ptr) \ 47 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 48 #define bf_set_le32(name, ptr, value) \ 49 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 50 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 51 ~(name##_MASK << name##_SHIFT))))) 52 #define bf_set(name, ptr, value) \ 53 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 54 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 55 56 struct dma_address { 57 uint32_t addr_lo; 58 uint32_t addr_hi; 59 }; 60 61 struct lpfc_sli_intf { 62 uint32_t word0; 63 #define lpfc_sli_intf_valid_SHIFT 29 64 #define lpfc_sli_intf_valid_MASK 0x00000007 65 #define lpfc_sli_intf_valid_WORD word0 66 #define LPFC_SLI_INTF_VALID 6 67 #define lpfc_sli_intf_sli_hint2_SHIFT 24 68 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 69 #define lpfc_sli_intf_sli_hint2_WORD word0 70 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 71 #define lpfc_sli_intf_sli_hint1_SHIFT 16 72 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 73 #define lpfc_sli_intf_sli_hint1_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 75 #define LPFC_SLI_INTF_SLI_HINT1_1 1 76 #define LPFC_SLI_INTF_SLI_HINT1_2 2 77 #define lpfc_sli_intf_if_type_SHIFT 12 78 #define lpfc_sli_intf_if_type_MASK 0x0000000F 79 #define lpfc_sli_intf_if_type_WORD word0 80 #define LPFC_SLI_INTF_IF_TYPE_0 0 81 #define LPFC_SLI_INTF_IF_TYPE_1 1 82 #define LPFC_SLI_INTF_IF_TYPE_2 2 83 #define lpfc_sli_intf_sli_family_SHIFT 8 84 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 85 #define lpfc_sli_intf_sli_family_WORD word0 86 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 87 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 88 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 89 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 90 #define lpfc_sli_intf_slirev_SHIFT 4 91 #define lpfc_sli_intf_slirev_MASK 0x0000000F 92 #define lpfc_sli_intf_slirev_WORD word0 93 #define LPFC_SLI_INTF_REV_SLI3 3 94 #define LPFC_SLI_INTF_REV_SLI4 4 95 #define lpfc_sli_intf_func_type_SHIFT 0 96 #define lpfc_sli_intf_func_type_MASK 0x00000001 97 #define lpfc_sli_intf_func_type_WORD word0 98 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 99 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 100 }; 101 102 #define LPFC_SLI4_MBX_EMBED true 103 #define LPFC_SLI4_MBX_NEMBED false 104 105 #define LPFC_SLI4_MB_WORD_COUNT 64 106 #define LPFC_MAX_MQ_PAGE 8 107 #define LPFC_MAX_WQ_PAGE 8 108 #define LPFC_MAX_CQ_PAGE 4 109 #define LPFC_MAX_EQ_PAGE 8 110 111 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 112 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 113 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 114 115 /* Define SLI4 Alignment requirements. */ 116 #define LPFC_ALIGN_16_BYTE 16 117 #define LPFC_ALIGN_64_BYTE 64 118 119 /* Define SLI4 specific definitions. */ 120 #define LPFC_MQ_CQE_BYTE_OFFSET 256 121 #define LPFC_MBX_CMD_HDR_LENGTH 16 122 #define LPFC_MBX_ERROR_RANGE 0x4000 123 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 124 #define LPFC_BMBX_BIT1_ADDR_LO 0 125 #define LPFC_RPI_HDR_COUNT 64 126 #define LPFC_HDR_TEMPLATE_SIZE 4096 127 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 128 #define LPFC_FCF_RECORD_WD_CNT 132 129 #define LPFC_ENTIRE_FCF_DATABASE 0 130 #define LPFC_DFLT_FCF_INDEX 0 131 132 /* Virtual function numbers */ 133 #define LPFC_VF0 0 134 #define LPFC_VF1 1 135 #define LPFC_VF2 2 136 #define LPFC_VF3 3 137 #define LPFC_VF4 4 138 #define LPFC_VF5 5 139 #define LPFC_VF6 6 140 #define LPFC_VF7 7 141 #define LPFC_VF8 8 142 #define LPFC_VF9 9 143 #define LPFC_VF10 10 144 #define LPFC_VF11 11 145 #define LPFC_VF12 12 146 #define LPFC_VF13 13 147 #define LPFC_VF14 14 148 #define LPFC_VF15 15 149 #define LPFC_VF16 16 150 #define LPFC_VF17 17 151 #define LPFC_VF18 18 152 #define LPFC_VF19 19 153 #define LPFC_VF20 20 154 #define LPFC_VF21 21 155 #define LPFC_VF22 22 156 #define LPFC_VF23 23 157 #define LPFC_VF24 24 158 #define LPFC_VF25 25 159 #define LPFC_VF26 26 160 #define LPFC_VF27 27 161 #define LPFC_VF28 28 162 #define LPFC_VF29 29 163 #define LPFC_VF30 30 164 #define LPFC_VF31 31 165 166 /* PCI function numbers */ 167 #define LPFC_PCI_FUNC0 0 168 #define LPFC_PCI_FUNC1 1 169 #define LPFC_PCI_FUNC2 2 170 #define LPFC_PCI_FUNC3 3 171 #define LPFC_PCI_FUNC4 4 172 173 /* Active interrupt test count */ 174 #define LPFC_ACT_INTR_CNT 4 175 176 /* Delay Multiplier constant */ 177 #define LPFC_DMULT_CONST 651042 178 #define LPFC_MIM_IMAX 636 179 #define LPFC_FP_DEF_IMAX 10000 180 #define LPFC_SP_DEF_IMAX 10000 181 182 /* PORT_CAPABILITIES constants. */ 183 #define LPFC_MAX_SUPPORTED_PAGES 8 184 185 struct ulp_bde64 { 186 union ULP_BDE_TUS { 187 uint32_t w; 188 struct { 189 #ifdef __BIG_ENDIAN_BITFIELD 190 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 191 VALUE !! */ 192 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 193 #else /* __LITTLE_ENDIAN_BITFIELD */ 194 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 195 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 196 VALUE !! */ 197 #endif 198 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 199 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 200 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 201 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 202 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 203 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 204 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 205 } f; 206 } tus; 207 uint32_t addrLow; 208 uint32_t addrHigh; 209 }; 210 211 struct lpfc_sli4_flags { 212 uint32_t word0; 213 #define lpfc_fip_flag_SHIFT 0 214 #define lpfc_fip_flag_MASK 0x00000001 215 #define lpfc_fip_flag_WORD word0 216 }; 217 218 struct sli4_bls_rsp { 219 uint32_t word0_rsvd; /* Word0 must be reserved */ 220 uint32_t word1; 221 #define lpfc_abts_orig_SHIFT 0 222 #define lpfc_abts_orig_MASK 0x00000001 223 #define lpfc_abts_orig_WORD word1 224 #define LPFC_ABTS_UNSOL_RSP 1 225 #define LPFC_ABTS_UNSOL_INT 0 226 uint32_t word2; 227 #define lpfc_abts_rxid_SHIFT 0 228 #define lpfc_abts_rxid_MASK 0x0000FFFF 229 #define lpfc_abts_rxid_WORD word2 230 #define lpfc_abts_oxid_SHIFT 16 231 #define lpfc_abts_oxid_MASK 0x0000FFFF 232 #define lpfc_abts_oxid_WORD word2 233 uint32_t word3; 234 #define lpfc_vndr_code_SHIFT 0 235 #define lpfc_vndr_code_MASK 0x000000FF 236 #define lpfc_vndr_code_WORD word3 237 #define lpfc_rsn_expln_SHIFT 8 238 #define lpfc_rsn_expln_MASK 0x000000FF 239 #define lpfc_rsn_expln_WORD word3 240 #define lpfc_rsn_code_SHIFT 16 241 #define lpfc_rsn_code_MASK 0x000000FF 242 #define lpfc_rsn_code_WORD word3 243 244 uint32_t word4; 245 uint32_t word5_rsvd; /* Word5 must be reserved */ 246 }; 247 248 /* event queue entry structure */ 249 struct lpfc_eqe { 250 uint32_t word0; 251 #define lpfc_eqe_resource_id_SHIFT 16 252 #define lpfc_eqe_resource_id_MASK 0x000000FF 253 #define lpfc_eqe_resource_id_WORD word0 254 #define lpfc_eqe_minor_code_SHIFT 4 255 #define lpfc_eqe_minor_code_MASK 0x00000FFF 256 #define lpfc_eqe_minor_code_WORD word0 257 #define lpfc_eqe_major_code_SHIFT 1 258 #define lpfc_eqe_major_code_MASK 0x00000007 259 #define lpfc_eqe_major_code_WORD word0 260 #define lpfc_eqe_valid_SHIFT 0 261 #define lpfc_eqe_valid_MASK 0x00000001 262 #define lpfc_eqe_valid_WORD word0 263 }; 264 265 /* completion queue entry structure (common fields for all cqe types) */ 266 struct lpfc_cqe { 267 uint32_t reserved0; 268 uint32_t reserved1; 269 uint32_t reserved2; 270 uint32_t word3; 271 #define lpfc_cqe_valid_SHIFT 31 272 #define lpfc_cqe_valid_MASK 0x00000001 273 #define lpfc_cqe_valid_WORD word3 274 #define lpfc_cqe_code_SHIFT 16 275 #define lpfc_cqe_code_MASK 0x000000FF 276 #define lpfc_cqe_code_WORD word3 277 }; 278 279 /* Completion Queue Entry Status Codes */ 280 #define CQE_STATUS_SUCCESS 0x0 281 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 282 #define CQE_STATUS_REMOTE_STOP 0x2 283 #define CQE_STATUS_LOCAL_REJECT 0x3 284 #define CQE_STATUS_NPORT_RJT 0x4 285 #define CQE_STATUS_FABRIC_RJT 0x5 286 #define CQE_STATUS_NPORT_BSY 0x6 287 #define CQE_STATUS_FABRIC_BSY 0x7 288 #define CQE_STATUS_INTERMED_RSP 0x8 289 #define CQE_STATUS_LS_RJT 0x9 290 #define CQE_STATUS_CMD_REJECT 0xb 291 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 292 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 293 294 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 295 #define CQE_HW_STATUS_NO_ERR 0x0 296 #define CQE_HW_STATUS_UNDERRUN 0x1 297 #define CQE_HW_STATUS_OVERRUN 0x2 298 299 /* Completion Queue Entry Codes */ 300 #define CQE_CODE_COMPL_WQE 0x1 301 #define CQE_CODE_RELEASE_WQE 0x2 302 #define CQE_CODE_RECEIVE 0x4 303 #define CQE_CODE_XRI_ABORTED 0x5 304 305 /* completion queue entry for wqe completions */ 306 struct lpfc_wcqe_complete { 307 uint32_t word0; 308 #define lpfc_wcqe_c_request_tag_SHIFT 16 309 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 310 #define lpfc_wcqe_c_request_tag_WORD word0 311 #define lpfc_wcqe_c_status_SHIFT 8 312 #define lpfc_wcqe_c_status_MASK 0x000000FF 313 #define lpfc_wcqe_c_status_WORD word0 314 #define lpfc_wcqe_c_hw_status_SHIFT 0 315 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 316 #define lpfc_wcqe_c_hw_status_WORD word0 317 uint32_t total_data_placed; 318 uint32_t parameter; 319 uint32_t word3; 320 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 321 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 322 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 323 #define lpfc_wcqe_c_xb_SHIFT 28 324 #define lpfc_wcqe_c_xb_MASK 0x00000001 325 #define lpfc_wcqe_c_xb_WORD word3 326 #define lpfc_wcqe_c_pv_SHIFT 27 327 #define lpfc_wcqe_c_pv_MASK 0x00000001 328 #define lpfc_wcqe_c_pv_WORD word3 329 #define lpfc_wcqe_c_priority_SHIFT 24 330 #define lpfc_wcqe_c_priority_MASK 0x00000007 331 #define lpfc_wcqe_c_priority_WORD word3 332 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 333 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 334 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 335 }; 336 337 /* completion queue entry for wqe release */ 338 struct lpfc_wcqe_release { 339 uint32_t reserved0; 340 uint32_t reserved1; 341 uint32_t word2; 342 #define lpfc_wcqe_r_wq_id_SHIFT 16 343 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 344 #define lpfc_wcqe_r_wq_id_WORD word2 345 #define lpfc_wcqe_r_wqe_index_SHIFT 0 346 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 347 #define lpfc_wcqe_r_wqe_index_WORD word2 348 uint32_t word3; 349 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 350 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 351 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 352 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 353 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 354 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 355 }; 356 357 struct sli4_wcqe_xri_aborted { 358 uint32_t word0; 359 #define lpfc_wcqe_xa_status_SHIFT 8 360 #define lpfc_wcqe_xa_status_MASK 0x000000FF 361 #define lpfc_wcqe_xa_status_WORD word0 362 uint32_t parameter; 363 uint32_t word2; 364 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 365 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 366 #define lpfc_wcqe_xa_remote_xid_WORD word2 367 #define lpfc_wcqe_xa_xri_SHIFT 0 368 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 369 #define lpfc_wcqe_xa_xri_WORD word2 370 uint32_t word3; 371 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 372 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 373 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 374 #define lpfc_wcqe_xa_ia_SHIFT 30 375 #define lpfc_wcqe_xa_ia_MASK 0x00000001 376 #define lpfc_wcqe_xa_ia_WORD word3 377 #define CQE_XRI_ABORTED_IA_REMOTE 0 378 #define CQE_XRI_ABORTED_IA_LOCAL 1 379 #define lpfc_wcqe_xa_br_SHIFT 29 380 #define lpfc_wcqe_xa_br_MASK 0x00000001 381 #define lpfc_wcqe_xa_br_WORD word3 382 #define CQE_XRI_ABORTED_BR_BA_ACC 0 383 #define CQE_XRI_ABORTED_BR_BA_RJT 1 384 #define lpfc_wcqe_xa_eo_SHIFT 28 385 #define lpfc_wcqe_xa_eo_MASK 0x00000001 386 #define lpfc_wcqe_xa_eo_WORD word3 387 #define CQE_XRI_ABORTED_EO_REMOTE 0 388 #define CQE_XRI_ABORTED_EO_LOCAL 1 389 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 390 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 391 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 392 }; 393 394 /* completion queue entry structure for rqe completion */ 395 struct lpfc_rcqe { 396 uint32_t word0; 397 #define lpfc_rcqe_bindex_SHIFT 16 398 #define lpfc_rcqe_bindex_MASK 0x0000FFF 399 #define lpfc_rcqe_bindex_WORD word0 400 #define lpfc_rcqe_status_SHIFT 8 401 #define lpfc_rcqe_status_MASK 0x000000FF 402 #define lpfc_rcqe_status_WORD word0 403 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 404 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 405 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 406 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 407 uint32_t reserved1; 408 uint32_t word2; 409 #define lpfc_rcqe_length_SHIFT 16 410 #define lpfc_rcqe_length_MASK 0x0000FFFF 411 #define lpfc_rcqe_length_WORD word2 412 #define lpfc_rcqe_rq_id_SHIFT 6 413 #define lpfc_rcqe_rq_id_MASK 0x000003FF 414 #define lpfc_rcqe_rq_id_WORD word2 415 #define lpfc_rcqe_fcf_id_SHIFT 0 416 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 417 #define lpfc_rcqe_fcf_id_WORD word2 418 uint32_t word3; 419 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 420 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 421 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 422 #define lpfc_rcqe_port_SHIFT 30 423 #define lpfc_rcqe_port_MASK 0x00000001 424 #define lpfc_rcqe_port_WORD word3 425 #define lpfc_rcqe_hdr_length_SHIFT 24 426 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 427 #define lpfc_rcqe_hdr_length_WORD word3 428 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 429 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 430 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 431 #define lpfc_rcqe_eof_SHIFT 8 432 #define lpfc_rcqe_eof_MASK 0x000000FF 433 #define lpfc_rcqe_eof_WORD word3 434 #define FCOE_EOFn 0x41 435 #define FCOE_EOFt 0x42 436 #define FCOE_EOFni 0x49 437 #define FCOE_EOFa 0x50 438 #define lpfc_rcqe_sof_SHIFT 0 439 #define lpfc_rcqe_sof_MASK 0x000000FF 440 #define lpfc_rcqe_sof_WORD word3 441 #define FCOE_SOFi2 0x2d 442 #define FCOE_SOFi3 0x2e 443 #define FCOE_SOFn2 0x35 444 #define FCOE_SOFn3 0x36 445 }; 446 447 struct lpfc_rqe { 448 uint32_t address_hi; 449 uint32_t address_lo; 450 }; 451 452 /* buffer descriptors */ 453 struct lpfc_bde4 { 454 uint32_t addr_hi; 455 uint32_t addr_lo; 456 uint32_t word2; 457 #define lpfc_bde4_last_SHIFT 31 458 #define lpfc_bde4_last_MASK 0x00000001 459 #define lpfc_bde4_last_WORD word2 460 #define lpfc_bde4_sge_offset_SHIFT 0 461 #define lpfc_bde4_sge_offset_MASK 0x000003FF 462 #define lpfc_bde4_sge_offset_WORD word2 463 uint32_t word3; 464 #define lpfc_bde4_length_SHIFT 0 465 #define lpfc_bde4_length_MASK 0x000000FF 466 #define lpfc_bde4_length_WORD word3 467 }; 468 469 struct lpfc_register { 470 uint32_t word0; 471 }; 472 473 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 474 #define LPFC_UERR_STATUS_HI 0x00A4 475 #define LPFC_UERR_STATUS_LO 0x00A0 476 #define LPFC_UE_MASK_HI 0x00AC 477 #define LPFC_UE_MASK_LO 0x00A8 478 479 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 480 #define LPFC_SLI_INTF 0x0058 481 482 #define LPFC_SLIPORT_IF2_SMPHR 0x0400 483 #define lpfc_port_smphr_perr_SHIFT 31 484 #define lpfc_port_smphr_perr_MASK 0x1 485 #define lpfc_port_smphr_perr_WORD word0 486 #define lpfc_port_smphr_sfi_SHIFT 30 487 #define lpfc_port_smphr_sfi_MASK 0x1 488 #define lpfc_port_smphr_sfi_WORD word0 489 #define lpfc_port_smphr_nip_SHIFT 29 490 #define lpfc_port_smphr_nip_MASK 0x1 491 #define lpfc_port_smphr_nip_WORD word0 492 #define lpfc_port_smphr_ipc_SHIFT 28 493 #define lpfc_port_smphr_ipc_MASK 0x1 494 #define lpfc_port_smphr_ipc_WORD word0 495 #define lpfc_port_smphr_scr1_SHIFT 27 496 #define lpfc_port_smphr_scr1_MASK 0x1 497 #define lpfc_port_smphr_scr1_WORD word0 498 #define lpfc_port_smphr_scr2_SHIFT 26 499 #define lpfc_port_smphr_scr2_MASK 0x1 500 #define lpfc_port_smphr_scr2_WORD word0 501 #define lpfc_port_smphr_host_scratch_SHIFT 16 502 #define lpfc_port_smphr_host_scratch_MASK 0xFF 503 #define lpfc_port_smphr_host_scratch_WORD word0 504 #define lpfc_port_smphr_port_status_SHIFT 0 505 #define lpfc_port_smphr_port_status_MASK 0xFFFF 506 #define lpfc_port_smphr_port_status_WORD word0 507 508 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 509 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 510 #define LPFC_POST_STAGE_HOST_RDY 0x0002 511 #define LPFC_POST_STAGE_BE_RESET 0x0003 512 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 513 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 514 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 515 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 516 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 517 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 518 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 519 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 520 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 521 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 522 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 523 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 524 #define LPFC_POST_STAGE_ARMFW_START 0x0800 525 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 526 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 527 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 528 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 529 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 530 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 531 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 532 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 533 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 534 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 535 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 536 #define LPFC_POST_STAGE_RC_DONE 0x0B07 537 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 538 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 539 #define LPFC_POST_STAGE_PORT_READY 0xC000 540 #define LPFC_POST_STAGE_PORT_UE 0xF000 541 542 #define LPFC_SLIPORT_STATUS 0x0404 543 #define lpfc_sliport_status_err_SHIFT 31 544 #define lpfc_sliport_status_err_MASK 0x1 545 #define lpfc_sliport_status_err_WORD word0 546 #define lpfc_sliport_status_end_SHIFT 30 547 #define lpfc_sliport_status_end_MASK 0x1 548 #define lpfc_sliport_status_end_WORD word0 549 #define lpfc_sliport_status_oti_SHIFT 29 550 #define lpfc_sliport_status_oti_MASK 0x1 551 #define lpfc_sliport_status_oti_WORD word0 552 #define lpfc_sliport_status_rn_SHIFT 24 553 #define lpfc_sliport_status_rn_MASK 0x1 554 #define lpfc_sliport_status_rn_WORD word0 555 #define lpfc_sliport_status_rdy_SHIFT 23 556 #define lpfc_sliport_status_rdy_MASK 0x1 557 #define lpfc_sliport_status_rdy_WORD word0 558 #define MAX_IF_TYPE_2_RESETS 1000 559 560 #define LPFC_SLIPORT_CNTRL 0x0408 561 #define lpfc_sliport_ctrl_end_SHIFT 30 562 #define lpfc_sliport_ctrl_end_MASK 0x1 563 #define lpfc_sliport_ctrl_end_WORD word0 564 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 565 #define LPFC_SLIPORT_BIG_ENDIAN 1 566 #define lpfc_sliport_ctrl_ip_SHIFT 27 567 #define lpfc_sliport_ctrl_ip_MASK 0x1 568 #define lpfc_sliport_ctrl_ip_WORD word0 569 #define LPFC_SLIPORT_INIT_PORT 1 570 571 #define LPFC_SLIPORT_ERR_1 0x040C 572 #define LPFC_SLIPORT_ERR_2 0x0410 573 574 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 575 * reside in BAR 2. 576 */ 577 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 578 579 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 580 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 581 582 #define LPFC_HST_ISR0 0x0C18 583 #define LPFC_HST_ISR1 0x0C1C 584 #define LPFC_HST_ISR2 0x0C20 585 #define LPFC_HST_ISR3 0x0C24 586 #define LPFC_HST_ISR4 0x0C28 587 588 #define LPFC_HST_IMR0 0x0C48 589 #define LPFC_HST_IMR1 0x0C4C 590 #define LPFC_HST_IMR2 0x0C50 591 #define LPFC_HST_IMR3 0x0C54 592 #define LPFC_HST_IMR4 0x0C58 593 594 #define LPFC_HST_ISCR0 0x0C78 595 #define LPFC_HST_ISCR1 0x0C7C 596 #define LPFC_HST_ISCR2 0x0C80 597 #define LPFC_HST_ISCR3 0x0C84 598 #define LPFC_HST_ISCR4 0x0C88 599 600 #define LPFC_SLI4_INTR0 BIT0 601 #define LPFC_SLI4_INTR1 BIT1 602 #define LPFC_SLI4_INTR2 BIT2 603 #define LPFC_SLI4_INTR3 BIT3 604 #define LPFC_SLI4_INTR4 BIT4 605 #define LPFC_SLI4_INTR5 BIT5 606 #define LPFC_SLI4_INTR6 BIT6 607 #define LPFC_SLI4_INTR7 BIT7 608 #define LPFC_SLI4_INTR8 BIT8 609 #define LPFC_SLI4_INTR9 BIT9 610 #define LPFC_SLI4_INTR10 BIT10 611 #define LPFC_SLI4_INTR11 BIT11 612 #define LPFC_SLI4_INTR12 BIT12 613 #define LPFC_SLI4_INTR13 BIT13 614 #define LPFC_SLI4_INTR14 BIT14 615 #define LPFC_SLI4_INTR15 BIT15 616 #define LPFC_SLI4_INTR16 BIT16 617 #define LPFC_SLI4_INTR17 BIT17 618 #define LPFC_SLI4_INTR18 BIT18 619 #define LPFC_SLI4_INTR19 BIT19 620 #define LPFC_SLI4_INTR20 BIT20 621 #define LPFC_SLI4_INTR21 BIT21 622 #define LPFC_SLI4_INTR22 BIT22 623 #define LPFC_SLI4_INTR23 BIT23 624 #define LPFC_SLI4_INTR24 BIT24 625 #define LPFC_SLI4_INTR25 BIT25 626 #define LPFC_SLI4_INTR26 BIT26 627 #define LPFC_SLI4_INTR27 BIT27 628 #define LPFC_SLI4_INTR28 BIT28 629 #define LPFC_SLI4_INTR29 BIT29 630 #define LPFC_SLI4_INTR30 BIT30 631 #define LPFC_SLI4_INTR31 BIT31 632 633 /* 634 * The Doorbell registers defined here exist in different BAR 635 * register sets depending on the UCNA Port's reported if_type 636 * value. For UCNA ports running SLI4 and if_type 0, they reside in 637 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 638 * BAR0. The offsets are the same so the driver must account for 639 * any base address difference. 640 */ 641 #define LPFC_RQ_DOORBELL 0x00A0 642 #define lpfc_rq_doorbell_num_posted_SHIFT 16 643 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 644 #define lpfc_rq_doorbell_num_posted_WORD word0 645 #define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */ 646 #define lpfc_rq_doorbell_id_SHIFT 0 647 #define lpfc_rq_doorbell_id_MASK 0xFFFF 648 #define lpfc_rq_doorbell_id_WORD word0 649 650 #define LPFC_WQ_DOORBELL 0x0040 651 #define lpfc_wq_doorbell_num_posted_SHIFT 24 652 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 653 #define lpfc_wq_doorbell_num_posted_WORD word0 654 #define lpfc_wq_doorbell_index_SHIFT 16 655 #define lpfc_wq_doorbell_index_MASK 0x00FF 656 #define lpfc_wq_doorbell_index_WORD word0 657 #define lpfc_wq_doorbell_id_SHIFT 0 658 #define lpfc_wq_doorbell_id_MASK 0xFFFF 659 #define lpfc_wq_doorbell_id_WORD word0 660 661 #define LPFC_EQCQ_DOORBELL 0x0120 662 #define lpfc_eqcq_doorbell_se_SHIFT 31 663 #define lpfc_eqcq_doorbell_se_MASK 0x0001 664 #define lpfc_eqcq_doorbell_se_WORD word0 665 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 666 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 667 #define lpfc_eqcq_doorbell_arm_SHIFT 29 668 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 669 #define lpfc_eqcq_doorbell_arm_WORD word0 670 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 671 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 672 #define lpfc_eqcq_doorbell_num_released_WORD word0 673 #define lpfc_eqcq_doorbell_qt_SHIFT 10 674 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 675 #define lpfc_eqcq_doorbell_qt_WORD word0 676 #define LPFC_QUEUE_TYPE_COMPLETION 0 677 #define LPFC_QUEUE_TYPE_EVENT 1 678 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 679 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 680 #define lpfc_eqcq_doorbell_eqci_WORD word0 681 #define lpfc_eqcq_doorbell_cqid_SHIFT 0 682 #define lpfc_eqcq_doorbell_cqid_MASK 0x03FF 683 #define lpfc_eqcq_doorbell_cqid_WORD word0 684 #define lpfc_eqcq_doorbell_eqid_SHIFT 0 685 #define lpfc_eqcq_doorbell_eqid_MASK 0x01FF 686 #define lpfc_eqcq_doorbell_eqid_WORD word0 687 688 #define LPFC_BMBX 0x0160 689 #define lpfc_bmbx_addr_SHIFT 2 690 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 691 #define lpfc_bmbx_addr_WORD word0 692 #define lpfc_bmbx_hi_SHIFT 1 693 #define lpfc_bmbx_hi_MASK 0x0001 694 #define lpfc_bmbx_hi_WORD word0 695 #define lpfc_bmbx_rdy_SHIFT 0 696 #define lpfc_bmbx_rdy_MASK 0x0001 697 #define lpfc_bmbx_rdy_WORD word0 698 699 #define LPFC_MQ_DOORBELL 0x0140 700 #define lpfc_mq_doorbell_num_posted_SHIFT 16 701 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 702 #define lpfc_mq_doorbell_num_posted_WORD word0 703 #define lpfc_mq_doorbell_id_SHIFT 0 704 #define lpfc_mq_doorbell_id_MASK 0xFFFF 705 #define lpfc_mq_doorbell_id_WORD word0 706 707 struct lpfc_sli4_cfg_mhdr { 708 uint32_t word1; 709 #define lpfc_mbox_hdr_emb_SHIFT 0 710 #define lpfc_mbox_hdr_emb_MASK 0x00000001 711 #define lpfc_mbox_hdr_emb_WORD word1 712 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 713 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 714 #define lpfc_mbox_hdr_sge_cnt_WORD word1 715 uint32_t payload_length; 716 uint32_t tag_lo; 717 uint32_t tag_hi; 718 uint32_t reserved5; 719 }; 720 721 union lpfc_sli4_cfg_shdr { 722 struct { 723 uint32_t word6; 724 #define lpfc_mbox_hdr_opcode_SHIFT 0 725 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 726 #define lpfc_mbox_hdr_opcode_WORD word6 727 #define lpfc_mbox_hdr_subsystem_SHIFT 8 728 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 729 #define lpfc_mbox_hdr_subsystem_WORD word6 730 #define lpfc_mbox_hdr_port_number_SHIFT 16 731 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 732 #define lpfc_mbox_hdr_port_number_WORD word6 733 #define lpfc_mbox_hdr_domain_SHIFT 24 734 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 735 #define lpfc_mbox_hdr_domain_WORD word6 736 uint32_t timeout; 737 uint32_t request_length; 738 uint32_t word9; 739 #define lpfc_mbox_hdr_version_SHIFT 0 740 #define lpfc_mbox_hdr_version_MASK 0x000000FF 741 #define lpfc_mbox_hdr_version_WORD word9 742 #define LPFC_Q_CREATE_VERSION_2 2 743 #define LPFC_Q_CREATE_VERSION_1 1 744 #define LPFC_Q_CREATE_VERSION_0 0 745 } request; 746 struct { 747 uint32_t word6; 748 #define lpfc_mbox_hdr_opcode_SHIFT 0 749 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 750 #define lpfc_mbox_hdr_opcode_WORD word6 751 #define lpfc_mbox_hdr_subsystem_SHIFT 8 752 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 753 #define lpfc_mbox_hdr_subsystem_WORD word6 754 #define lpfc_mbox_hdr_domain_SHIFT 24 755 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 756 #define lpfc_mbox_hdr_domain_WORD word6 757 uint32_t word7; 758 #define lpfc_mbox_hdr_status_SHIFT 0 759 #define lpfc_mbox_hdr_status_MASK 0x000000FF 760 #define lpfc_mbox_hdr_status_WORD word7 761 #define lpfc_mbox_hdr_add_status_SHIFT 8 762 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 763 #define lpfc_mbox_hdr_add_status_WORD word7 764 uint32_t response_length; 765 uint32_t actual_response_length; 766 } response; 767 }; 768 769 /* Mailbox structures */ 770 struct mbox_header { 771 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 772 union lpfc_sli4_cfg_shdr cfg_shdr; 773 }; 774 775 /* Subsystem Definitions */ 776 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 777 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 778 779 /* Device Specific Definitions */ 780 781 /* The HOST ENDIAN defines are in Big Endian format. */ 782 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 783 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 784 785 /* Common Opcodes */ 786 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 787 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 788 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 789 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 790 #define LPFC_MBOX_OPCODE_NOP 0x21 791 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 792 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 793 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 794 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 795 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 796 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 797 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 798 799 /* FCoE Opcodes */ 800 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 801 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 802 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 803 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 804 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 805 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 806 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 807 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 808 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 809 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 810 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 811 812 /* Mailbox command structures */ 813 struct eq_context { 814 uint32_t word0; 815 #define lpfc_eq_context_size_SHIFT 31 816 #define lpfc_eq_context_size_MASK 0x00000001 817 #define lpfc_eq_context_size_WORD word0 818 #define LPFC_EQE_SIZE_4 0x0 819 #define LPFC_EQE_SIZE_16 0x1 820 #define lpfc_eq_context_valid_SHIFT 29 821 #define lpfc_eq_context_valid_MASK 0x00000001 822 #define lpfc_eq_context_valid_WORD word0 823 uint32_t word1; 824 #define lpfc_eq_context_count_SHIFT 26 825 #define lpfc_eq_context_count_MASK 0x00000003 826 #define lpfc_eq_context_count_WORD word1 827 #define LPFC_EQ_CNT_256 0x0 828 #define LPFC_EQ_CNT_512 0x1 829 #define LPFC_EQ_CNT_1024 0x2 830 #define LPFC_EQ_CNT_2048 0x3 831 #define LPFC_EQ_CNT_4096 0x4 832 uint32_t word2; 833 #define lpfc_eq_context_delay_multi_SHIFT 13 834 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 835 #define lpfc_eq_context_delay_multi_WORD word2 836 uint32_t reserved3; 837 }; 838 839 struct sgl_page_pairs { 840 uint32_t sgl_pg0_addr_lo; 841 uint32_t sgl_pg0_addr_hi; 842 uint32_t sgl_pg1_addr_lo; 843 uint32_t sgl_pg1_addr_hi; 844 }; 845 846 struct lpfc_mbx_post_sgl_pages { 847 struct mbox_header header; 848 uint32_t word0; 849 #define lpfc_post_sgl_pages_xri_SHIFT 0 850 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 851 #define lpfc_post_sgl_pages_xri_WORD word0 852 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 853 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 854 #define lpfc_post_sgl_pages_xricnt_WORD word0 855 struct sgl_page_pairs sgl_pg_pairs[1]; 856 }; 857 858 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 859 struct lpfc_mbx_post_uembed_sgl_page1 { 860 union lpfc_sli4_cfg_shdr cfg_shdr; 861 uint32_t word0; 862 struct sgl_page_pairs sgl_pg_pairs; 863 }; 864 865 struct lpfc_mbx_sge { 866 uint32_t pa_lo; 867 uint32_t pa_hi; 868 uint32_t length; 869 }; 870 871 struct lpfc_mbx_nembed_cmd { 872 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 873 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 874 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 875 }; 876 877 struct lpfc_mbx_nembed_sge_virt { 878 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 879 }; 880 881 struct lpfc_mbx_eq_create { 882 struct mbox_header header; 883 union { 884 struct { 885 uint32_t word0; 886 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 887 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 888 #define lpfc_mbx_eq_create_num_pages_WORD word0 889 struct eq_context context; 890 struct dma_address page[LPFC_MAX_EQ_PAGE]; 891 } request; 892 struct { 893 uint32_t word0; 894 #define lpfc_mbx_eq_create_q_id_SHIFT 0 895 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 896 #define lpfc_mbx_eq_create_q_id_WORD word0 897 } response; 898 } u; 899 }; 900 901 struct lpfc_mbx_eq_destroy { 902 struct mbox_header header; 903 union { 904 struct { 905 uint32_t word0; 906 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 907 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 908 #define lpfc_mbx_eq_destroy_q_id_WORD word0 909 } request; 910 struct { 911 uint32_t word0; 912 } response; 913 } u; 914 }; 915 916 struct lpfc_mbx_nop { 917 struct mbox_header header; 918 uint32_t context[2]; 919 }; 920 921 struct cq_context { 922 uint32_t word0; 923 #define lpfc_cq_context_event_SHIFT 31 924 #define lpfc_cq_context_event_MASK 0x00000001 925 #define lpfc_cq_context_event_WORD word0 926 #define lpfc_cq_context_valid_SHIFT 29 927 #define lpfc_cq_context_valid_MASK 0x00000001 928 #define lpfc_cq_context_valid_WORD word0 929 #define lpfc_cq_context_count_SHIFT 27 930 #define lpfc_cq_context_count_MASK 0x00000003 931 #define lpfc_cq_context_count_WORD word0 932 #define LPFC_CQ_CNT_256 0x0 933 #define LPFC_CQ_CNT_512 0x1 934 #define LPFC_CQ_CNT_1024 0x2 935 uint32_t word1; 936 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 937 #define lpfc_cq_eq_id_MASK 0x000000FF 938 #define lpfc_cq_eq_id_WORD word1 939 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 940 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 941 #define lpfc_cq_eq_id_2_WORD word1 942 uint32_t reserved0; 943 uint32_t reserved1; 944 }; 945 946 struct lpfc_mbx_cq_create { 947 struct mbox_header header; 948 union { 949 struct { 950 uint32_t word0; 951 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 952 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 953 #define lpfc_mbx_cq_create_page_size_WORD word0 954 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 955 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 956 #define lpfc_mbx_cq_create_num_pages_WORD word0 957 struct cq_context context; 958 struct dma_address page[LPFC_MAX_CQ_PAGE]; 959 } request; 960 struct { 961 uint32_t word0; 962 #define lpfc_mbx_cq_create_q_id_SHIFT 0 963 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 964 #define lpfc_mbx_cq_create_q_id_WORD word0 965 } response; 966 } u; 967 }; 968 969 struct lpfc_mbx_cq_destroy { 970 struct mbox_header header; 971 union { 972 struct { 973 uint32_t word0; 974 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 975 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 976 #define lpfc_mbx_cq_destroy_q_id_WORD word0 977 } request; 978 struct { 979 uint32_t word0; 980 } response; 981 } u; 982 }; 983 984 struct wq_context { 985 uint32_t reserved0; 986 uint32_t reserved1; 987 uint32_t reserved2; 988 uint32_t reserved3; 989 }; 990 991 struct lpfc_mbx_wq_create { 992 struct mbox_header header; 993 union { 994 struct { /* Version 0 Request */ 995 uint32_t word0; 996 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 997 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 998 #define lpfc_mbx_wq_create_num_pages_WORD word0 999 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1000 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1001 #define lpfc_mbx_wq_create_cq_id_WORD word0 1002 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1003 } request; 1004 struct { /* Version 1 Request */ 1005 uint32_t word0; /* Word 0 is the same as in v0 */ 1006 uint32_t word1; 1007 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1008 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1009 #define lpfc_mbx_wq_create_page_size_WORD word1 1010 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1011 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1012 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1013 #define LPFC_WQ_WQE_SIZE_64 0x5 1014 #define LPFC_WQ_WQE_SIZE_128 0x6 1015 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1016 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1017 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1018 uint32_t word2; 1019 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1020 } request_1; 1021 struct { 1022 uint32_t word0; 1023 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1024 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1025 #define lpfc_mbx_wq_create_q_id_WORD word0 1026 } response; 1027 } u; 1028 }; 1029 1030 struct lpfc_mbx_wq_destroy { 1031 struct mbox_header header; 1032 union { 1033 struct { 1034 uint32_t word0; 1035 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1036 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1037 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1038 } request; 1039 struct { 1040 uint32_t word0; 1041 } response; 1042 } u; 1043 }; 1044 1045 #define LPFC_HDR_BUF_SIZE 128 1046 #define LPFC_DATA_BUF_SIZE 2048 1047 struct rq_context { 1048 uint32_t word0; 1049 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1050 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1051 #define lpfc_rq_context_rqe_count_WORD word0 1052 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1053 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1054 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1055 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1056 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1057 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1058 #define lpfc_rq_context_rqe_count_1_WORD word0 1059 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1060 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1061 #define lpfc_rq_context_rqe_size_WORD word0 1062 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1063 #define lpfc_rq_context_page_size_MASK 0x000000FF 1064 #define lpfc_rq_context_page_size_WORD word0 1065 uint32_t reserved1; 1066 uint32_t word2; 1067 #define lpfc_rq_context_cq_id_SHIFT 16 1068 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1069 #define lpfc_rq_context_cq_id_WORD word2 1070 #define lpfc_rq_context_buf_size_SHIFT 0 1071 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1072 #define lpfc_rq_context_buf_size_WORD word2 1073 uint32_t buffer_size; /* Version 1 Only */ 1074 }; 1075 1076 struct lpfc_mbx_rq_create { 1077 struct mbox_header header; 1078 union { 1079 struct { 1080 uint32_t word0; 1081 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1082 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1083 #define lpfc_mbx_rq_create_num_pages_WORD word0 1084 struct rq_context context; 1085 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1086 } request; 1087 struct { 1088 uint32_t word0; 1089 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1090 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1091 #define lpfc_mbx_rq_create_q_id_WORD word0 1092 } response; 1093 } u; 1094 }; 1095 1096 struct lpfc_mbx_rq_destroy { 1097 struct mbox_header header; 1098 union { 1099 struct { 1100 uint32_t word0; 1101 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1102 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1103 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1104 } request; 1105 struct { 1106 uint32_t word0; 1107 } response; 1108 } u; 1109 }; 1110 1111 struct mq_context { 1112 uint32_t word0; 1113 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1114 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1115 #define lpfc_mq_context_cq_id_WORD word0 1116 #define lpfc_mq_context_ring_size_SHIFT 16 1117 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1118 #define lpfc_mq_context_ring_size_WORD word0 1119 #define LPFC_MQ_RING_SIZE_16 0x5 1120 #define LPFC_MQ_RING_SIZE_32 0x6 1121 #define LPFC_MQ_RING_SIZE_64 0x7 1122 #define LPFC_MQ_RING_SIZE_128 0x8 1123 uint32_t word1; 1124 #define lpfc_mq_context_valid_SHIFT 31 1125 #define lpfc_mq_context_valid_MASK 0x00000001 1126 #define lpfc_mq_context_valid_WORD word1 1127 uint32_t reserved2; 1128 uint32_t reserved3; 1129 }; 1130 1131 struct lpfc_mbx_mq_create { 1132 struct mbox_header header; 1133 union { 1134 struct { 1135 uint32_t word0; 1136 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1137 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1138 #define lpfc_mbx_mq_create_num_pages_WORD word0 1139 struct mq_context context; 1140 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1141 } request; 1142 struct { 1143 uint32_t word0; 1144 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1145 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1146 #define lpfc_mbx_mq_create_q_id_WORD word0 1147 } response; 1148 } u; 1149 }; 1150 1151 struct lpfc_mbx_mq_create_ext { 1152 struct mbox_header header; 1153 union { 1154 struct { 1155 uint32_t word0; 1156 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1157 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1158 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1159 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1160 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1161 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1162 uint32_t async_evt_bmap; 1163 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1164 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1165 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1166 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1167 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1168 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1169 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1170 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1171 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1172 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1173 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1174 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1175 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1176 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1177 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1178 struct mq_context context; 1179 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1180 } request; 1181 struct { 1182 uint32_t word0; 1183 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1184 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1185 #define lpfc_mbx_mq_create_q_id_WORD word0 1186 } response; 1187 } u; 1188 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1189 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1190 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1191 }; 1192 1193 struct lpfc_mbx_mq_destroy { 1194 struct mbox_header header; 1195 union { 1196 struct { 1197 uint32_t word0; 1198 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1199 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1200 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1201 } request; 1202 struct { 1203 uint32_t word0; 1204 } response; 1205 } u; 1206 }; 1207 1208 struct lpfc_mbx_post_hdr_tmpl { 1209 struct mbox_header header; 1210 uint32_t word10; 1211 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1212 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1213 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1214 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1215 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1216 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1217 uint32_t rpi_paddr_lo; 1218 uint32_t rpi_paddr_hi; 1219 }; 1220 1221 struct sli4_sge { /* SLI-4 */ 1222 uint32_t addr_hi; 1223 uint32_t addr_lo; 1224 1225 uint32_t word2; 1226 #define lpfc_sli4_sge_offset_SHIFT 0 /* Offset of buffer - Not used*/ 1227 #define lpfc_sli4_sge_offset_MASK 0x00FFFFFF 1228 #define lpfc_sli4_sge_offset_WORD word2 1229 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets 1230 this flag !! */ 1231 #define lpfc_sli4_sge_last_MASK 0x00000001 1232 #define lpfc_sli4_sge_last_WORD word2 1233 uint32_t sge_len; 1234 }; 1235 1236 struct fcf_record { 1237 uint32_t max_rcv_size; 1238 uint32_t fka_adv_period; 1239 uint32_t fip_priority; 1240 uint32_t word3; 1241 #define lpfc_fcf_record_mac_0_SHIFT 0 1242 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1243 #define lpfc_fcf_record_mac_0_WORD word3 1244 #define lpfc_fcf_record_mac_1_SHIFT 8 1245 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1246 #define lpfc_fcf_record_mac_1_WORD word3 1247 #define lpfc_fcf_record_mac_2_SHIFT 16 1248 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1249 #define lpfc_fcf_record_mac_2_WORD word3 1250 #define lpfc_fcf_record_mac_3_SHIFT 24 1251 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1252 #define lpfc_fcf_record_mac_3_WORD word3 1253 uint32_t word4; 1254 #define lpfc_fcf_record_mac_4_SHIFT 0 1255 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1256 #define lpfc_fcf_record_mac_4_WORD word4 1257 #define lpfc_fcf_record_mac_5_SHIFT 8 1258 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1259 #define lpfc_fcf_record_mac_5_WORD word4 1260 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1261 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1262 #define lpfc_fcf_record_fcf_avail_WORD word4 1263 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1264 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1265 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1266 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1267 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1268 uint32_t word5; 1269 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1270 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1271 #define lpfc_fcf_record_fab_name_0_WORD word5 1272 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1273 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1274 #define lpfc_fcf_record_fab_name_1_WORD word5 1275 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1276 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1277 #define lpfc_fcf_record_fab_name_2_WORD word5 1278 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1279 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1280 #define lpfc_fcf_record_fab_name_3_WORD word5 1281 uint32_t word6; 1282 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1283 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1284 #define lpfc_fcf_record_fab_name_4_WORD word6 1285 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1286 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1287 #define lpfc_fcf_record_fab_name_5_WORD word6 1288 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1289 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1290 #define lpfc_fcf_record_fab_name_6_WORD word6 1291 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1292 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1293 #define lpfc_fcf_record_fab_name_7_WORD word6 1294 uint32_t word7; 1295 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1296 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1297 #define lpfc_fcf_record_fc_map_0_WORD word7 1298 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1299 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1300 #define lpfc_fcf_record_fc_map_1_WORD word7 1301 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1302 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1303 #define lpfc_fcf_record_fc_map_2_WORD word7 1304 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1305 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1306 #define lpfc_fcf_record_fcf_valid_WORD word7 1307 uint32_t word8; 1308 #define lpfc_fcf_record_fcf_index_SHIFT 0 1309 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1310 #define lpfc_fcf_record_fcf_index_WORD word8 1311 #define lpfc_fcf_record_fcf_state_SHIFT 16 1312 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1313 #define lpfc_fcf_record_fcf_state_WORD word8 1314 uint8_t vlan_bitmap[512]; 1315 uint32_t word137; 1316 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1317 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1318 #define lpfc_fcf_record_switch_name_0_WORD word137 1319 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1320 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1321 #define lpfc_fcf_record_switch_name_1_WORD word137 1322 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1323 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1324 #define lpfc_fcf_record_switch_name_2_WORD word137 1325 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1326 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1327 #define lpfc_fcf_record_switch_name_3_WORD word137 1328 uint32_t word138; 1329 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1330 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1331 #define lpfc_fcf_record_switch_name_4_WORD word138 1332 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1333 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1334 #define lpfc_fcf_record_switch_name_5_WORD word138 1335 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1336 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1337 #define lpfc_fcf_record_switch_name_6_WORD word138 1338 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1339 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1340 #define lpfc_fcf_record_switch_name_7_WORD word138 1341 }; 1342 1343 struct lpfc_mbx_read_fcf_tbl { 1344 union lpfc_sli4_cfg_shdr cfg_shdr; 1345 union { 1346 struct { 1347 uint32_t word10; 1348 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1349 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1350 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1351 } request; 1352 struct { 1353 uint32_t eventag; 1354 } response; 1355 } u; 1356 uint32_t word11; 1357 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1358 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1359 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1360 }; 1361 1362 struct lpfc_mbx_add_fcf_tbl_entry { 1363 union lpfc_sli4_cfg_shdr cfg_shdr; 1364 uint32_t word10; 1365 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1366 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1367 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1368 struct lpfc_mbx_sge fcf_sge; 1369 }; 1370 1371 struct lpfc_mbx_del_fcf_tbl_entry { 1372 struct mbox_header header; 1373 uint32_t word10; 1374 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1375 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1376 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1377 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1378 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1379 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1380 }; 1381 1382 struct lpfc_mbx_redisc_fcf_tbl { 1383 struct mbox_header header; 1384 uint32_t word10; 1385 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1386 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1387 #define lpfc_mbx_redisc_fcf_count_WORD word10 1388 uint32_t resvd; 1389 uint32_t word12; 1390 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1391 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1392 #define lpfc_mbx_redisc_fcf_index_WORD word12 1393 }; 1394 1395 struct lpfc_mbx_query_fw_cfg { 1396 struct mbox_header header; 1397 uint32_t config_number; 1398 uint32_t asic_rev; 1399 uint32_t phys_port; 1400 uint32_t function_mode; 1401 /* firmware Function Mode */ 1402 #define lpfc_function_mode_toe_SHIFT 0 1403 #define lpfc_function_mode_toe_MASK 0x00000001 1404 #define lpfc_function_mode_toe_WORD function_mode 1405 #define lpfc_function_mode_nic_SHIFT 1 1406 #define lpfc_function_mode_nic_MASK 0x00000001 1407 #define lpfc_function_mode_nic_WORD function_mode 1408 #define lpfc_function_mode_rdma_SHIFT 2 1409 #define lpfc_function_mode_rdma_MASK 0x00000001 1410 #define lpfc_function_mode_rdma_WORD function_mode 1411 #define lpfc_function_mode_vm_SHIFT 3 1412 #define lpfc_function_mode_vm_MASK 0x00000001 1413 #define lpfc_function_mode_vm_WORD function_mode 1414 #define lpfc_function_mode_iscsi_i_SHIFT 4 1415 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1416 #define lpfc_function_mode_iscsi_i_WORD function_mode 1417 #define lpfc_function_mode_iscsi_t_SHIFT 5 1418 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1419 #define lpfc_function_mode_iscsi_t_WORD function_mode 1420 #define lpfc_function_mode_fcoe_i_SHIFT 6 1421 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1422 #define lpfc_function_mode_fcoe_i_WORD function_mode 1423 #define lpfc_function_mode_fcoe_t_SHIFT 7 1424 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1425 #define lpfc_function_mode_fcoe_t_WORD function_mode 1426 #define lpfc_function_mode_dal_SHIFT 8 1427 #define lpfc_function_mode_dal_MASK 0x00000001 1428 #define lpfc_function_mode_dal_WORD function_mode 1429 #define lpfc_function_mode_lro_SHIFT 9 1430 #define lpfc_function_mode_lro_MASK 0x00000001 1431 #define lpfc_function_mode_lro_WORD function_mode 1432 #define lpfc_function_mode_flex10_SHIFT 10 1433 #define lpfc_function_mode_flex10_MASK 0x00000001 1434 #define lpfc_function_mode_flex10_WORD function_mode 1435 #define lpfc_function_mode_ncsi_SHIFT 11 1436 #define lpfc_function_mode_ncsi_MASK 0x00000001 1437 #define lpfc_function_mode_ncsi_WORD function_mode 1438 }; 1439 1440 /* Status field for embedded SLI_CONFIG mailbox command */ 1441 #define STATUS_SUCCESS 0x0 1442 #define STATUS_FAILED 0x1 1443 #define STATUS_ILLEGAL_REQUEST 0x2 1444 #define STATUS_ILLEGAL_FIELD 0x3 1445 #define STATUS_INSUFFICIENT_BUFFER 0x4 1446 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1447 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1448 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1449 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1450 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1451 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1452 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1453 #define STATUS_ASSERT_FAILED 0x1e 1454 #define STATUS_INVALID_SESSION 0x1f 1455 #define STATUS_INVALID_CONNECTION 0x20 1456 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1457 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1458 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1459 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1460 #define STATUS_FLASHROM_READ_FAILED 0x27 1461 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1462 #define STATUS_ERROR_ACITMAIN 0x2a 1463 #define STATUS_REBOOT_REQUIRED 0x2c 1464 #define STATUS_FCF_IN_USE 0x3a 1465 #define STATUS_FCF_TABLE_EMPTY 0x43 1466 1467 struct lpfc_mbx_sli4_config { 1468 struct mbox_header header; 1469 }; 1470 1471 struct lpfc_mbx_init_vfi { 1472 uint32_t word1; 1473 #define lpfc_init_vfi_vr_SHIFT 31 1474 #define lpfc_init_vfi_vr_MASK 0x00000001 1475 #define lpfc_init_vfi_vr_WORD word1 1476 #define lpfc_init_vfi_vt_SHIFT 30 1477 #define lpfc_init_vfi_vt_MASK 0x00000001 1478 #define lpfc_init_vfi_vt_WORD word1 1479 #define lpfc_init_vfi_vf_SHIFT 29 1480 #define lpfc_init_vfi_vf_MASK 0x00000001 1481 #define lpfc_init_vfi_vf_WORD word1 1482 #define lpfc_init_vfi_vp_SHIFT 28 1483 #define lpfc_init_vfi_vp_MASK 0x00000001 1484 #define lpfc_init_vfi_vp_WORD word1 1485 #define lpfc_init_vfi_vfi_SHIFT 0 1486 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1487 #define lpfc_init_vfi_vfi_WORD word1 1488 uint32_t word2; 1489 #define lpfc_init_vfi_vpi_SHIFT 16 1490 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1491 #define lpfc_init_vfi_vpi_WORD word2 1492 #define lpfc_init_vfi_fcfi_SHIFT 0 1493 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1494 #define lpfc_init_vfi_fcfi_WORD word2 1495 uint32_t word3; 1496 #define lpfc_init_vfi_pri_SHIFT 13 1497 #define lpfc_init_vfi_pri_MASK 0x00000007 1498 #define lpfc_init_vfi_pri_WORD word3 1499 #define lpfc_init_vfi_vf_id_SHIFT 1 1500 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1501 #define lpfc_init_vfi_vf_id_WORD word3 1502 uint32_t word4; 1503 #define lpfc_init_vfi_hop_count_SHIFT 24 1504 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1505 #define lpfc_init_vfi_hop_count_WORD word4 1506 }; 1507 1508 struct lpfc_mbx_reg_vfi { 1509 uint32_t word1; 1510 #define lpfc_reg_vfi_vp_SHIFT 28 1511 #define lpfc_reg_vfi_vp_MASK 0x00000001 1512 #define lpfc_reg_vfi_vp_WORD word1 1513 #define lpfc_reg_vfi_vfi_SHIFT 0 1514 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1515 #define lpfc_reg_vfi_vfi_WORD word1 1516 uint32_t word2; 1517 #define lpfc_reg_vfi_vpi_SHIFT 16 1518 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1519 #define lpfc_reg_vfi_vpi_WORD word2 1520 #define lpfc_reg_vfi_fcfi_SHIFT 0 1521 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1522 #define lpfc_reg_vfi_fcfi_WORD word2 1523 uint32_t wwn[2]; 1524 struct ulp_bde64 bde; 1525 uint32_t e_d_tov; 1526 uint32_t r_a_tov; 1527 uint32_t word10; 1528 #define lpfc_reg_vfi_nport_id_SHIFT 0 1529 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1530 #define lpfc_reg_vfi_nport_id_WORD word10 1531 }; 1532 1533 struct lpfc_mbx_init_vpi { 1534 uint32_t word1; 1535 #define lpfc_init_vpi_vfi_SHIFT 16 1536 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1537 #define lpfc_init_vpi_vfi_WORD word1 1538 #define lpfc_init_vpi_vpi_SHIFT 0 1539 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1540 #define lpfc_init_vpi_vpi_WORD word1 1541 }; 1542 1543 struct lpfc_mbx_read_vpi { 1544 uint32_t word1_rsvd; 1545 uint32_t word2; 1546 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1547 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1548 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1549 uint32_t word3_rsvd; 1550 uint32_t word4; 1551 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1552 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1553 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1554 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1555 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1556 #define lpfc_mbx_read_vpi_pb_WORD word4 1557 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1558 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1559 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1560 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1561 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1562 #define lpfc_mbx_read_vpi_ns_WORD word4 1563 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1564 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1565 #define lpfc_mbx_read_vpi_hl_WORD word4 1566 uint32_t word5_rsvd; 1567 uint32_t word6; 1568 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1569 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1570 #define lpfc_mbx_read_vpi_vpi_WORD word6 1571 uint32_t word7; 1572 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1573 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1574 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1575 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1576 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1577 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1578 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1579 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1580 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1581 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1582 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1583 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1584 uint32_t word8; 1585 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1586 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1587 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1588 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1589 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1590 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1591 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1592 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1593 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1594 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1595 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1596 #define lpfc_mbx_read_vpi_vv_WORD word8 1597 }; 1598 1599 struct lpfc_mbx_unreg_vfi { 1600 uint32_t word1_rsvd; 1601 uint32_t word2; 1602 #define lpfc_unreg_vfi_vfi_SHIFT 0 1603 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1604 #define lpfc_unreg_vfi_vfi_WORD word2 1605 }; 1606 1607 struct lpfc_mbx_resume_rpi { 1608 uint32_t word1; 1609 #define lpfc_resume_rpi_index_SHIFT 0 1610 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1611 #define lpfc_resume_rpi_index_WORD word1 1612 #define lpfc_resume_rpi_ii_SHIFT 30 1613 #define lpfc_resume_rpi_ii_MASK 0x00000003 1614 #define lpfc_resume_rpi_ii_WORD word1 1615 #define RESUME_INDEX_RPI 0 1616 #define RESUME_INDEX_VPI 1 1617 #define RESUME_INDEX_VFI 2 1618 #define RESUME_INDEX_FCFI 3 1619 uint32_t event_tag; 1620 }; 1621 1622 #define REG_FCF_INVALID_QID 0xFFFF 1623 struct lpfc_mbx_reg_fcfi { 1624 uint32_t word1; 1625 #define lpfc_reg_fcfi_info_index_SHIFT 0 1626 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 1627 #define lpfc_reg_fcfi_info_index_WORD word1 1628 #define lpfc_reg_fcfi_fcfi_SHIFT 16 1629 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 1630 #define lpfc_reg_fcfi_fcfi_WORD word1 1631 uint32_t word2; 1632 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 1633 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 1634 #define lpfc_reg_fcfi_rq_id1_WORD word2 1635 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 1636 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 1637 #define lpfc_reg_fcfi_rq_id0_WORD word2 1638 uint32_t word3; 1639 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 1640 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 1641 #define lpfc_reg_fcfi_rq_id3_WORD word3 1642 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 1643 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 1644 #define lpfc_reg_fcfi_rq_id2_WORD word3 1645 uint32_t word4; 1646 #define lpfc_reg_fcfi_type_match0_SHIFT 24 1647 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 1648 #define lpfc_reg_fcfi_type_match0_WORD word4 1649 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 1650 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 1651 #define lpfc_reg_fcfi_type_mask0_WORD word4 1652 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 1653 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 1654 #define lpfc_reg_fcfi_rctl_match0_WORD word4 1655 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 1656 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 1657 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 1658 uint32_t word5; 1659 #define lpfc_reg_fcfi_type_match1_SHIFT 24 1660 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 1661 #define lpfc_reg_fcfi_type_match1_WORD word5 1662 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 1663 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 1664 #define lpfc_reg_fcfi_type_mask1_WORD word5 1665 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 1666 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 1667 #define lpfc_reg_fcfi_rctl_match1_WORD word5 1668 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 1669 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 1670 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 1671 uint32_t word6; 1672 #define lpfc_reg_fcfi_type_match2_SHIFT 24 1673 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 1674 #define lpfc_reg_fcfi_type_match2_WORD word6 1675 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 1676 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 1677 #define lpfc_reg_fcfi_type_mask2_WORD word6 1678 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 1679 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 1680 #define lpfc_reg_fcfi_rctl_match2_WORD word6 1681 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 1682 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 1683 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 1684 uint32_t word7; 1685 #define lpfc_reg_fcfi_type_match3_SHIFT 24 1686 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 1687 #define lpfc_reg_fcfi_type_match3_WORD word7 1688 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 1689 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 1690 #define lpfc_reg_fcfi_type_mask3_WORD word7 1691 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 1692 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 1693 #define lpfc_reg_fcfi_rctl_match3_WORD word7 1694 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 1695 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 1696 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 1697 uint32_t word8; 1698 #define lpfc_reg_fcfi_mam_SHIFT 13 1699 #define lpfc_reg_fcfi_mam_MASK 0x00000003 1700 #define lpfc_reg_fcfi_mam_WORD word8 1701 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 1702 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 1703 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 1704 #define lpfc_reg_fcfi_vv_SHIFT 12 1705 #define lpfc_reg_fcfi_vv_MASK 0x00000001 1706 #define lpfc_reg_fcfi_vv_WORD word8 1707 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 1708 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 1709 #define lpfc_reg_fcfi_vlan_tag_WORD word8 1710 }; 1711 1712 struct lpfc_mbx_unreg_fcfi { 1713 uint32_t word1_rsv; 1714 uint32_t word2; 1715 #define lpfc_unreg_fcfi_SHIFT 0 1716 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 1717 #define lpfc_unreg_fcfi_WORD word2 1718 }; 1719 1720 struct lpfc_mbx_read_rev { 1721 uint32_t word1; 1722 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 1723 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 1724 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 1725 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 1726 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 1727 #define lpfc_mbx_rd_rev_fcoe_WORD word1 1728 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 1729 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 1730 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 1731 #define LPFC_PREDCBX_CEE_MODE 0 1732 #define LPFC_DCBX_CEE_MODE 1 1733 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 1734 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 1735 #define lpfc_mbx_rd_rev_vpd_WORD word1 1736 uint32_t first_hw_rev; 1737 uint32_t second_hw_rev; 1738 uint32_t word4_rsvd; 1739 uint32_t third_hw_rev; 1740 uint32_t word6; 1741 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 1742 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 1743 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 1744 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 1745 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 1746 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 1747 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 1748 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 1749 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 1750 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 1751 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 1752 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 1753 uint32_t word7_rsvd; 1754 uint32_t fw_id_rev; 1755 uint8_t fw_name[16]; 1756 uint32_t ulp_fw_id_rev; 1757 uint8_t ulp_fw_name[16]; 1758 uint32_t word18_47_rsvd[30]; 1759 uint32_t word48; 1760 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 1761 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 1762 #define lpfc_mbx_rd_rev_avail_len_WORD word48 1763 uint32_t vpd_paddr_low; 1764 uint32_t vpd_paddr_high; 1765 uint32_t avail_vpd_len; 1766 uint32_t rsvd_52_63[12]; 1767 }; 1768 1769 struct lpfc_mbx_read_config { 1770 uint32_t word1; 1771 #define lpfc_mbx_rd_conf_max_bbc_SHIFT 0 1772 #define lpfc_mbx_rd_conf_max_bbc_MASK 0x000000FF 1773 #define lpfc_mbx_rd_conf_max_bbc_WORD word1 1774 #define lpfc_mbx_rd_conf_init_bbc_SHIFT 8 1775 #define lpfc_mbx_rd_conf_init_bbc_MASK 0x000000FF 1776 #define lpfc_mbx_rd_conf_init_bbc_WORD word1 1777 uint32_t word2; 1778 #define lpfc_mbx_rd_conf_nport_did_SHIFT 0 1779 #define lpfc_mbx_rd_conf_nport_did_MASK 0x00FFFFFF 1780 #define lpfc_mbx_rd_conf_nport_did_WORD word2 1781 #define lpfc_mbx_rd_conf_topology_SHIFT 24 1782 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 1783 #define lpfc_mbx_rd_conf_topology_WORD word2 1784 uint32_t word3; 1785 #define lpfc_mbx_rd_conf_ao_SHIFT 0 1786 #define lpfc_mbx_rd_conf_ao_MASK 0x00000001 1787 #define lpfc_mbx_rd_conf_ao_WORD word3 1788 #define lpfc_mbx_rd_conf_bb_scn_SHIFT 8 1789 #define lpfc_mbx_rd_conf_bb_scn_MASK 0x0000000F 1790 #define lpfc_mbx_rd_conf_bb_scn_WORD word3 1791 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT 12 1792 #define lpfc_mbx_rd_conf_cbb_scn_MASK 0x0000000F 1793 #define lpfc_mbx_rd_conf_cbb_scn_WORD word3 1794 #define lpfc_mbx_rd_conf_mc_SHIFT 29 1795 #define lpfc_mbx_rd_conf_mc_MASK 0x00000001 1796 #define lpfc_mbx_rd_conf_mc_WORD word3 1797 uint32_t word4; 1798 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 1799 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 1800 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 1801 uint32_t word5; 1802 #define lpfc_mbx_rd_conf_lp_tov_SHIFT 0 1803 #define lpfc_mbx_rd_conf_lp_tov_MASK 0x0000FFFF 1804 #define lpfc_mbx_rd_conf_lp_tov_WORD word5 1805 uint32_t word6; 1806 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 1807 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 1808 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 1809 uint32_t word7; 1810 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT 0 1811 #define lpfc_mbx_rd_conf_r_t_tov_MASK 0x000000FF 1812 #define lpfc_mbx_rd_conf_r_t_tov_WORD word7 1813 uint32_t word8; 1814 #define lpfc_mbx_rd_conf_al_tov_SHIFT 0 1815 #define lpfc_mbx_rd_conf_al_tov_MASK 0x0000000F 1816 #define lpfc_mbx_rd_conf_al_tov_WORD word8 1817 uint32_t word9; 1818 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 1819 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 1820 #define lpfc_mbx_rd_conf_lmt_WORD word9 1821 uint32_t word10; 1822 #define lpfc_mbx_rd_conf_max_alpa_SHIFT 0 1823 #define lpfc_mbx_rd_conf_max_alpa_MASK 0x000000FF 1824 #define lpfc_mbx_rd_conf_max_alpa_WORD word10 1825 uint32_t word11_rsvd; 1826 uint32_t word12; 1827 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 1828 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 1829 #define lpfc_mbx_rd_conf_xri_base_WORD word12 1830 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 1831 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 1832 #define lpfc_mbx_rd_conf_xri_count_WORD word12 1833 uint32_t word13; 1834 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 1835 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 1836 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 1837 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 1838 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 1839 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 1840 uint32_t word14; 1841 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 1842 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 1843 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 1844 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 1845 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 1846 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 1847 uint32_t word15; 1848 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 1849 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 1850 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 1851 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 1852 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 1853 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 1854 uint32_t word16; 1855 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT 0 1856 #define lpfc_mbx_rd_conf_fcfi_base_MASK 0x0000FFFF 1857 #define lpfc_mbx_rd_conf_fcfi_base_WORD word16 1858 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 1859 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 1860 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 1861 uint32_t word17; 1862 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 1863 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 1864 #define lpfc_mbx_rd_conf_rq_count_WORD word17 1865 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 1866 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 1867 #define lpfc_mbx_rd_conf_eq_count_WORD word17 1868 uint32_t word18; 1869 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 1870 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 1871 #define lpfc_mbx_rd_conf_wq_count_WORD word18 1872 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 1873 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 1874 #define lpfc_mbx_rd_conf_cq_count_WORD word18 1875 }; 1876 1877 struct lpfc_mbx_request_features { 1878 uint32_t word1; 1879 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 1880 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 1881 #define lpfc_mbx_rq_ftr_qry_WORD word1 1882 uint32_t word2; 1883 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 1884 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 1885 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 1886 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 1887 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 1888 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 1889 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 1890 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 1891 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 1892 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 1893 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 1894 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 1895 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 1896 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 1897 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 1898 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 1899 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 1900 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 1901 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 1902 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 1903 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 1904 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 1905 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 1906 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 1907 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 1908 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 1909 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 1910 uint32_t word3; 1911 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 1912 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 1913 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 1914 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 1915 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 1916 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 1917 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 1918 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 1919 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 1920 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 1921 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 1922 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 1923 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 1924 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 1925 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 1926 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 1927 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 1928 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 1929 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 1930 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 1931 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 1932 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 1933 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 1934 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 1935 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 1936 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 1937 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 1938 }; 1939 1940 struct lpfc_mbx_supp_pages { 1941 uint32_t word1; 1942 #define qs_SHIFT 0 1943 #define qs_MASK 0x00000001 1944 #define qs_WORD word1 1945 #define wr_SHIFT 1 1946 #define wr_MASK 0x00000001 1947 #define wr_WORD word1 1948 #define pf_SHIFT 8 1949 #define pf_MASK 0x000000ff 1950 #define pf_WORD word1 1951 #define cpn_SHIFT 16 1952 #define cpn_MASK 0x000000ff 1953 #define cpn_WORD word1 1954 uint32_t word2; 1955 #define list_offset_SHIFT 0 1956 #define list_offset_MASK 0x000000ff 1957 #define list_offset_WORD word2 1958 #define next_offset_SHIFT 8 1959 #define next_offset_MASK 0x000000ff 1960 #define next_offset_WORD word2 1961 #define elem_cnt_SHIFT 16 1962 #define elem_cnt_MASK 0x000000ff 1963 #define elem_cnt_WORD word2 1964 uint32_t word3; 1965 #define pn_0_SHIFT 24 1966 #define pn_0_MASK 0x000000ff 1967 #define pn_0_WORD word3 1968 #define pn_1_SHIFT 16 1969 #define pn_1_MASK 0x000000ff 1970 #define pn_1_WORD word3 1971 #define pn_2_SHIFT 8 1972 #define pn_2_MASK 0x000000ff 1973 #define pn_2_WORD word3 1974 #define pn_3_SHIFT 0 1975 #define pn_3_MASK 0x000000ff 1976 #define pn_3_WORD word3 1977 uint32_t word4; 1978 #define pn_4_SHIFT 24 1979 #define pn_4_MASK 0x000000ff 1980 #define pn_4_WORD word4 1981 #define pn_5_SHIFT 16 1982 #define pn_5_MASK 0x000000ff 1983 #define pn_5_WORD word4 1984 #define pn_6_SHIFT 8 1985 #define pn_6_MASK 0x000000ff 1986 #define pn_6_WORD word4 1987 #define pn_7_SHIFT 0 1988 #define pn_7_MASK 0x000000ff 1989 #define pn_7_WORD word4 1990 uint32_t rsvd[27]; 1991 #define LPFC_SUPP_PAGES 0 1992 #define LPFC_BLOCK_GUARD_PROFILES 1 1993 #define LPFC_SLI4_PARAMETERS 2 1994 }; 1995 1996 struct lpfc_mbx_pc_sli4_params { 1997 uint32_t word1; 1998 #define qs_SHIFT 0 1999 #define qs_MASK 0x00000001 2000 #define qs_WORD word1 2001 #define wr_SHIFT 1 2002 #define wr_MASK 0x00000001 2003 #define wr_WORD word1 2004 #define pf_SHIFT 8 2005 #define pf_MASK 0x000000ff 2006 #define pf_WORD word1 2007 #define cpn_SHIFT 16 2008 #define cpn_MASK 0x000000ff 2009 #define cpn_WORD word1 2010 uint32_t word2; 2011 #define if_type_SHIFT 0 2012 #define if_type_MASK 0x00000007 2013 #define if_type_WORD word2 2014 #define sli_rev_SHIFT 4 2015 #define sli_rev_MASK 0x0000000f 2016 #define sli_rev_WORD word2 2017 #define sli_family_SHIFT 8 2018 #define sli_family_MASK 0x000000ff 2019 #define sli_family_WORD word2 2020 #define featurelevel_1_SHIFT 16 2021 #define featurelevel_1_MASK 0x000000ff 2022 #define featurelevel_1_WORD word2 2023 #define featurelevel_2_SHIFT 24 2024 #define featurelevel_2_MASK 0x0000001f 2025 #define featurelevel_2_WORD word2 2026 uint32_t word3; 2027 #define fcoe_SHIFT 0 2028 #define fcoe_MASK 0x00000001 2029 #define fcoe_WORD word3 2030 #define fc_SHIFT 1 2031 #define fc_MASK 0x00000001 2032 #define fc_WORD word3 2033 #define nic_SHIFT 2 2034 #define nic_MASK 0x00000001 2035 #define nic_WORD word3 2036 #define iscsi_SHIFT 3 2037 #define iscsi_MASK 0x00000001 2038 #define iscsi_WORD word3 2039 #define rdma_SHIFT 4 2040 #define rdma_MASK 0x00000001 2041 #define rdma_WORD word3 2042 uint32_t sge_supp_len; 2043 #define SLI4_PAGE_SIZE 4096 2044 uint32_t word5; 2045 #define if_page_sz_SHIFT 0 2046 #define if_page_sz_MASK 0x0000ffff 2047 #define if_page_sz_WORD word5 2048 #define loopbk_scope_SHIFT 24 2049 #define loopbk_scope_MASK 0x0000000f 2050 #define loopbk_scope_WORD word5 2051 #define rq_db_window_SHIFT 28 2052 #define rq_db_window_MASK 0x0000000f 2053 #define rq_db_window_WORD word5 2054 uint32_t word6; 2055 #define eq_pages_SHIFT 0 2056 #define eq_pages_MASK 0x0000000f 2057 #define eq_pages_WORD word6 2058 #define eqe_size_SHIFT 8 2059 #define eqe_size_MASK 0x000000ff 2060 #define eqe_size_WORD word6 2061 uint32_t word7; 2062 #define cq_pages_SHIFT 0 2063 #define cq_pages_MASK 0x0000000f 2064 #define cq_pages_WORD word7 2065 #define cqe_size_SHIFT 8 2066 #define cqe_size_MASK 0x000000ff 2067 #define cqe_size_WORD word7 2068 uint32_t word8; 2069 #define mq_pages_SHIFT 0 2070 #define mq_pages_MASK 0x0000000f 2071 #define mq_pages_WORD word8 2072 #define mqe_size_SHIFT 8 2073 #define mqe_size_MASK 0x000000ff 2074 #define mqe_size_WORD word8 2075 #define mq_elem_cnt_SHIFT 16 2076 #define mq_elem_cnt_MASK 0x000000ff 2077 #define mq_elem_cnt_WORD word8 2078 uint32_t word9; 2079 #define wq_pages_SHIFT 0 2080 #define wq_pages_MASK 0x0000ffff 2081 #define wq_pages_WORD word9 2082 #define wqe_size_SHIFT 8 2083 #define wqe_size_MASK 0x000000ff 2084 #define wqe_size_WORD word9 2085 uint32_t word10; 2086 #define rq_pages_SHIFT 0 2087 #define rq_pages_MASK 0x0000ffff 2088 #define rq_pages_WORD word10 2089 #define rqe_size_SHIFT 8 2090 #define rqe_size_MASK 0x000000ff 2091 #define rqe_size_WORD word10 2092 uint32_t word11; 2093 #define hdr_pages_SHIFT 0 2094 #define hdr_pages_MASK 0x0000000f 2095 #define hdr_pages_WORD word11 2096 #define hdr_size_SHIFT 8 2097 #define hdr_size_MASK 0x0000000f 2098 #define hdr_size_WORD word11 2099 #define hdr_pp_align_SHIFT 16 2100 #define hdr_pp_align_MASK 0x0000ffff 2101 #define hdr_pp_align_WORD word11 2102 uint32_t word12; 2103 #define sgl_pages_SHIFT 0 2104 #define sgl_pages_MASK 0x0000000f 2105 #define sgl_pages_WORD word12 2106 #define sgl_pp_align_SHIFT 16 2107 #define sgl_pp_align_MASK 0x0000ffff 2108 #define sgl_pp_align_WORD word12 2109 uint32_t rsvd_13_63[51]; 2110 }; 2111 2112 struct lpfc_sli4_parameters { 2113 uint32_t word0; 2114 #define cfg_prot_type_SHIFT 0 2115 #define cfg_prot_type_MASK 0x000000FF 2116 #define cfg_prot_type_WORD word0 2117 uint32_t word1; 2118 #define cfg_ft_SHIFT 0 2119 #define cfg_ft_MASK 0x00000001 2120 #define cfg_ft_WORD word1 2121 #define cfg_sli_rev_SHIFT 4 2122 #define cfg_sli_rev_MASK 0x0000000f 2123 #define cfg_sli_rev_WORD word1 2124 #define cfg_sli_family_SHIFT 8 2125 #define cfg_sli_family_MASK 0x0000000f 2126 #define cfg_sli_family_WORD word1 2127 #define cfg_if_type_SHIFT 12 2128 #define cfg_if_type_MASK 0x0000000f 2129 #define cfg_if_type_WORD word1 2130 #define cfg_sli_hint_1_SHIFT 16 2131 #define cfg_sli_hint_1_MASK 0x000000ff 2132 #define cfg_sli_hint_1_WORD word1 2133 #define cfg_sli_hint_2_SHIFT 24 2134 #define cfg_sli_hint_2_MASK 0x0000001f 2135 #define cfg_sli_hint_2_WORD word1 2136 uint32_t word2; 2137 uint32_t word3; 2138 uint32_t word4; 2139 #define cfg_cqv_SHIFT 14 2140 #define cfg_cqv_MASK 0x00000003 2141 #define cfg_cqv_WORD word4 2142 uint32_t word5; 2143 uint32_t word6; 2144 #define cfg_mqv_SHIFT 14 2145 #define cfg_mqv_MASK 0x00000003 2146 #define cfg_mqv_WORD word6 2147 uint32_t word7; 2148 uint32_t word8; 2149 #define cfg_wqv_SHIFT 14 2150 #define cfg_wqv_MASK 0x00000003 2151 #define cfg_wqv_WORD word8 2152 uint32_t word9; 2153 uint32_t word10; 2154 #define cfg_rqv_SHIFT 14 2155 #define cfg_rqv_MASK 0x00000003 2156 #define cfg_rqv_WORD word10 2157 uint32_t word11; 2158 #define cfg_rq_db_window_SHIFT 28 2159 #define cfg_rq_db_window_MASK 0x0000000f 2160 #define cfg_rq_db_window_WORD word11 2161 uint32_t word12; 2162 #define cfg_fcoe_SHIFT 0 2163 #define cfg_fcoe_MASK 0x00000001 2164 #define cfg_fcoe_WORD word12 2165 #define cfg_phwq_SHIFT 15 2166 #define cfg_phwq_MASK 0x00000001 2167 #define cfg_phwq_WORD word12 2168 #define cfg_loopbk_scope_SHIFT 28 2169 #define cfg_loopbk_scope_MASK 0x0000000f 2170 #define cfg_loopbk_scope_WORD word12 2171 uint32_t sge_supp_len; 2172 uint32_t word14; 2173 #define cfg_sgl_page_cnt_SHIFT 0 2174 #define cfg_sgl_page_cnt_MASK 0x0000000f 2175 #define cfg_sgl_page_cnt_WORD word14 2176 #define cfg_sgl_page_size_SHIFT 8 2177 #define cfg_sgl_page_size_MASK 0x000000ff 2178 #define cfg_sgl_page_size_WORD word14 2179 #define cfg_sgl_pp_align_SHIFT 16 2180 #define cfg_sgl_pp_align_MASK 0x000000ff 2181 #define cfg_sgl_pp_align_WORD word14 2182 uint32_t word15; 2183 uint32_t word16; 2184 uint32_t word17; 2185 uint32_t word18; 2186 uint32_t word19; 2187 }; 2188 2189 struct lpfc_mbx_get_sli4_parameters { 2190 struct mbox_header header; 2191 struct lpfc_sli4_parameters sli4_parameters; 2192 }; 2193 2194 /* Mailbox Completion Queue Error Messages */ 2195 #define MB_CQE_STATUS_SUCCESS 0x0 2196 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2197 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2198 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2199 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2200 #define MB_CQE_STATUS_DMA_FAILED 0x5 2201 2202 /* mailbox queue entry structure */ 2203 struct lpfc_mqe { 2204 uint32_t word0; 2205 #define lpfc_mqe_status_SHIFT 16 2206 #define lpfc_mqe_status_MASK 0x0000FFFF 2207 #define lpfc_mqe_status_WORD word0 2208 #define lpfc_mqe_command_SHIFT 8 2209 #define lpfc_mqe_command_MASK 0x000000FF 2210 #define lpfc_mqe_command_WORD word0 2211 union { 2212 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2213 /* sli4 mailbox commands */ 2214 struct lpfc_mbx_sli4_config sli4_config; 2215 struct lpfc_mbx_init_vfi init_vfi; 2216 struct lpfc_mbx_reg_vfi reg_vfi; 2217 struct lpfc_mbx_reg_vfi unreg_vfi; 2218 struct lpfc_mbx_init_vpi init_vpi; 2219 struct lpfc_mbx_resume_rpi resume_rpi; 2220 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2221 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2222 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2223 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2224 struct lpfc_mbx_reg_fcfi reg_fcfi; 2225 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2226 struct lpfc_mbx_mq_create mq_create; 2227 struct lpfc_mbx_mq_create_ext mq_create_ext; 2228 struct lpfc_mbx_eq_create eq_create; 2229 struct lpfc_mbx_cq_create cq_create; 2230 struct lpfc_mbx_wq_create wq_create; 2231 struct lpfc_mbx_rq_create rq_create; 2232 struct lpfc_mbx_mq_destroy mq_destroy; 2233 struct lpfc_mbx_eq_destroy eq_destroy; 2234 struct lpfc_mbx_cq_destroy cq_destroy; 2235 struct lpfc_mbx_wq_destroy wq_destroy; 2236 struct lpfc_mbx_rq_destroy rq_destroy; 2237 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 2238 struct lpfc_mbx_nembed_cmd nembed_cmd; 2239 struct lpfc_mbx_read_rev read_rev; 2240 struct lpfc_mbx_read_vpi read_vpi; 2241 struct lpfc_mbx_read_config rd_config; 2242 struct lpfc_mbx_request_features req_ftrs; 2243 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 2244 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 2245 struct lpfc_mbx_supp_pages supp_pages; 2246 struct lpfc_mbx_pc_sli4_params sli4_params; 2247 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 2248 struct lpfc_mbx_nop nop; 2249 } un; 2250 }; 2251 2252 struct lpfc_mcqe { 2253 uint32_t word0; 2254 #define lpfc_mcqe_status_SHIFT 0 2255 #define lpfc_mcqe_status_MASK 0x0000FFFF 2256 #define lpfc_mcqe_status_WORD word0 2257 #define lpfc_mcqe_ext_status_SHIFT 16 2258 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 2259 #define lpfc_mcqe_ext_status_WORD word0 2260 uint32_t mcqe_tag0; 2261 uint32_t mcqe_tag1; 2262 uint32_t trailer; 2263 #define lpfc_trailer_valid_SHIFT 31 2264 #define lpfc_trailer_valid_MASK 0x00000001 2265 #define lpfc_trailer_valid_WORD trailer 2266 #define lpfc_trailer_async_SHIFT 30 2267 #define lpfc_trailer_async_MASK 0x00000001 2268 #define lpfc_trailer_async_WORD trailer 2269 #define lpfc_trailer_hpi_SHIFT 29 2270 #define lpfc_trailer_hpi_MASK 0x00000001 2271 #define lpfc_trailer_hpi_WORD trailer 2272 #define lpfc_trailer_completed_SHIFT 28 2273 #define lpfc_trailer_completed_MASK 0x00000001 2274 #define lpfc_trailer_completed_WORD trailer 2275 #define lpfc_trailer_consumed_SHIFT 27 2276 #define lpfc_trailer_consumed_MASK 0x00000001 2277 #define lpfc_trailer_consumed_WORD trailer 2278 #define lpfc_trailer_type_SHIFT 16 2279 #define lpfc_trailer_type_MASK 0x000000FF 2280 #define lpfc_trailer_type_WORD trailer 2281 #define lpfc_trailer_code_SHIFT 8 2282 #define lpfc_trailer_code_MASK 0x000000FF 2283 #define lpfc_trailer_code_WORD trailer 2284 #define LPFC_TRAILER_CODE_LINK 0x1 2285 #define LPFC_TRAILER_CODE_FCOE 0x2 2286 #define LPFC_TRAILER_CODE_DCBX 0x3 2287 #define LPFC_TRAILER_CODE_GRP5 0x5 2288 #define LPFC_TRAILER_CODE_FC 0x10 2289 #define LPFC_TRAILER_CODE_SLI 0x11 2290 }; 2291 2292 struct lpfc_acqe_link { 2293 uint32_t word0; 2294 #define lpfc_acqe_link_speed_SHIFT 24 2295 #define lpfc_acqe_link_speed_MASK 0x000000FF 2296 #define lpfc_acqe_link_speed_WORD word0 2297 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 2298 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 2299 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 2300 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 2301 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 2302 #define lpfc_acqe_link_duplex_SHIFT 16 2303 #define lpfc_acqe_link_duplex_MASK 0x000000FF 2304 #define lpfc_acqe_link_duplex_WORD word0 2305 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 2306 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 2307 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 2308 #define lpfc_acqe_link_status_SHIFT 8 2309 #define lpfc_acqe_link_status_MASK 0x000000FF 2310 #define lpfc_acqe_link_status_WORD word0 2311 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 2312 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 2313 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2314 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2315 #define lpfc_acqe_link_type_SHIFT 6 2316 #define lpfc_acqe_link_type_MASK 0x00000003 2317 #define lpfc_acqe_link_type_WORD word0 2318 #define lpfc_acqe_link_number_SHIFT 0 2319 #define lpfc_acqe_link_number_MASK 0x0000003F 2320 #define lpfc_acqe_link_number_WORD word0 2321 uint32_t word1; 2322 #define lpfc_acqe_link_fault_SHIFT 0 2323 #define lpfc_acqe_link_fault_MASK 0x000000FF 2324 #define lpfc_acqe_link_fault_WORD word1 2325 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 2326 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 2327 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 2328 #define lpfc_acqe_logical_link_speed_SHIFT 16 2329 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 2330 #define lpfc_acqe_logical_link_speed_WORD word1 2331 uint32_t event_tag; 2332 uint32_t trailer; 2333 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 2334 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 2335 }; 2336 2337 struct lpfc_acqe_fip { 2338 uint32_t index; 2339 uint32_t word1; 2340 #define lpfc_acqe_fip_fcf_count_SHIFT 0 2341 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 2342 #define lpfc_acqe_fip_fcf_count_WORD word1 2343 #define lpfc_acqe_fip_event_type_SHIFT 16 2344 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 2345 #define lpfc_acqe_fip_event_type_WORD word1 2346 uint32_t event_tag; 2347 uint32_t trailer; 2348 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 2349 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 2350 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 2351 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 2352 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 2353 }; 2354 2355 struct lpfc_acqe_dcbx { 2356 uint32_t tlv_ttl; 2357 uint32_t reserved; 2358 uint32_t event_tag; 2359 uint32_t trailer; 2360 }; 2361 2362 struct lpfc_acqe_grp5 { 2363 uint32_t word0; 2364 #define lpfc_acqe_grp5_type_SHIFT 6 2365 #define lpfc_acqe_grp5_type_MASK 0x00000003 2366 #define lpfc_acqe_grp5_type_WORD word0 2367 #define lpfc_acqe_grp5_number_SHIFT 0 2368 #define lpfc_acqe_grp5_number_MASK 0x0000003F 2369 #define lpfc_acqe_grp5_number_WORD word0 2370 uint32_t word1; 2371 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 2372 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 2373 #define lpfc_acqe_grp5_llink_spd_WORD word1 2374 uint32_t event_tag; 2375 uint32_t trailer; 2376 }; 2377 2378 struct lpfc_acqe_fc_la { 2379 uint32_t word0; 2380 #define lpfc_acqe_fc_la_speed_SHIFT 24 2381 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 2382 #define lpfc_acqe_fc_la_speed_WORD word0 2383 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 2384 #define LPFC_FC_LA_SPEED_1G 0x1 2385 #define LPFC_FC_LA_SPEED_2G 0x2 2386 #define LPFC_FC_LA_SPEED_4G 0x4 2387 #define LPFC_FC_LA_SPEED_8G 0x8 2388 #define LPFC_FC_LA_SPEED_10G 0xA 2389 #define LPFC_FC_LA_SPEED_16G 0x10 2390 #define lpfc_acqe_fc_la_topology_SHIFT 16 2391 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 2392 #define lpfc_acqe_fc_la_topology_WORD word0 2393 #define LPFC_FC_LA_TOP_UNKOWN 0x0 2394 #define LPFC_FC_LA_TOP_P2P 0x1 2395 #define LPFC_FC_LA_TOP_FCAL 0x2 2396 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 2397 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 2398 #define lpfc_acqe_fc_la_att_type_SHIFT 8 2399 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 2400 #define lpfc_acqe_fc_la_att_type_WORD word0 2401 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 2402 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 2403 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 2404 #define lpfc_acqe_fc_la_port_type_SHIFT 6 2405 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 2406 #define lpfc_acqe_fc_la_port_type_WORD word0 2407 #define LPFC_LINK_TYPE_ETHERNET 0x0 2408 #define LPFC_LINK_TYPE_FC 0x1 2409 #define lpfc_acqe_fc_la_port_number_SHIFT 0 2410 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 2411 #define lpfc_acqe_fc_la_port_number_WORD word0 2412 uint32_t word1; 2413 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 2414 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 2415 #define lpfc_acqe_fc_la_llink_spd_WORD word1 2416 #define lpfc_acqe_fc_la_fault_SHIFT 0 2417 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 2418 #define lpfc_acqe_fc_la_fault_WORD word1 2419 #define LPFC_FC_LA_FAULT_NONE 0x0 2420 #define LPFC_FC_LA_FAULT_LOCAL 0x1 2421 #define LPFC_FC_LA_FAULT_REMOTE 0x2 2422 uint32_t event_tag; 2423 uint32_t trailer; 2424 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 2425 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 2426 }; 2427 2428 struct lpfc_acqe_sli { 2429 uint32_t event_data1; 2430 uint32_t event_data2; 2431 uint32_t reserved; 2432 uint32_t trailer; 2433 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 2434 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 2435 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 2436 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 2437 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 2438 }; 2439 2440 /* 2441 * Define the bootstrap mailbox (bmbx) region used to communicate 2442 * mailbox command between the host and port. The mailbox consists 2443 * of a payload area of 256 bytes and a completion queue of length 2444 * 16 bytes. 2445 */ 2446 struct lpfc_bmbx_create { 2447 struct lpfc_mqe mqe; 2448 struct lpfc_mcqe mcqe; 2449 }; 2450 2451 #define SGL_ALIGN_SZ 64 2452 #define SGL_PAGE_SIZE 4096 2453 /* align SGL addr on a size boundary - adjust address up */ 2454 #define NO_XRI ((uint16_t)-1) 2455 2456 struct wqe_common { 2457 uint32_t word6; 2458 #define wqe_xri_tag_SHIFT 0 2459 #define wqe_xri_tag_MASK 0x0000FFFF 2460 #define wqe_xri_tag_WORD word6 2461 #define wqe_ctxt_tag_SHIFT 16 2462 #define wqe_ctxt_tag_MASK 0x0000FFFF 2463 #define wqe_ctxt_tag_WORD word6 2464 uint32_t word7; 2465 #define wqe_ct_SHIFT 2 2466 #define wqe_ct_MASK 0x00000003 2467 #define wqe_ct_WORD word7 2468 #define wqe_status_SHIFT 4 2469 #define wqe_status_MASK 0x0000000f 2470 #define wqe_status_WORD word7 2471 #define wqe_cmnd_SHIFT 8 2472 #define wqe_cmnd_MASK 0x000000ff 2473 #define wqe_cmnd_WORD word7 2474 #define wqe_class_SHIFT 16 2475 #define wqe_class_MASK 0x00000007 2476 #define wqe_class_WORD word7 2477 #define wqe_pu_SHIFT 20 2478 #define wqe_pu_MASK 0x00000003 2479 #define wqe_pu_WORD word7 2480 #define wqe_erp_SHIFT 22 2481 #define wqe_erp_MASK 0x00000001 2482 #define wqe_erp_WORD word7 2483 #define wqe_lnk_SHIFT 23 2484 #define wqe_lnk_MASK 0x00000001 2485 #define wqe_lnk_WORD word7 2486 #define wqe_tmo_SHIFT 24 2487 #define wqe_tmo_MASK 0x000000ff 2488 #define wqe_tmo_WORD word7 2489 uint32_t abort_tag; /* word 8 in WQE */ 2490 uint32_t word9; 2491 #define wqe_reqtag_SHIFT 0 2492 #define wqe_reqtag_MASK 0x0000FFFF 2493 #define wqe_reqtag_WORD word9 2494 #define wqe_rcvoxid_SHIFT 16 2495 #define wqe_rcvoxid_MASK 0x0000FFFF 2496 #define wqe_rcvoxid_WORD word9 2497 uint32_t word10; 2498 #define wqe_ebde_cnt_SHIFT 0 2499 #define wqe_ebde_cnt_MASK 0x0000000f 2500 #define wqe_ebde_cnt_WORD word10 2501 #define wqe_lenloc_SHIFT 7 2502 #define wqe_lenloc_MASK 0x00000003 2503 #define wqe_lenloc_WORD word10 2504 #define LPFC_WQE_LENLOC_NONE 0 2505 #define LPFC_WQE_LENLOC_WORD3 1 2506 #define LPFC_WQE_LENLOC_WORD12 2 2507 #define LPFC_WQE_LENLOC_WORD4 3 2508 #define wqe_qosd_SHIFT 9 2509 #define wqe_qosd_MASK 0x00000001 2510 #define wqe_qosd_WORD word10 2511 #define wqe_xbl_SHIFT 11 2512 #define wqe_xbl_MASK 0x00000001 2513 #define wqe_xbl_WORD word10 2514 #define wqe_iod_SHIFT 13 2515 #define wqe_iod_MASK 0x00000001 2516 #define wqe_iod_WORD word10 2517 #define LPFC_WQE_IOD_WRITE 0 2518 #define LPFC_WQE_IOD_READ 1 2519 #define wqe_dbde_SHIFT 14 2520 #define wqe_dbde_MASK 0x00000001 2521 #define wqe_dbde_WORD word10 2522 #define wqe_wqes_SHIFT 15 2523 #define wqe_wqes_MASK 0x00000001 2524 #define wqe_wqes_WORD word10 2525 /* Note that this field overlaps above fields */ 2526 #define wqe_wqid_SHIFT 1 2527 #define wqe_wqid_MASK 0x0000007f 2528 #define wqe_wqid_WORD word10 2529 #define wqe_pri_SHIFT 16 2530 #define wqe_pri_MASK 0x00000007 2531 #define wqe_pri_WORD word10 2532 #define wqe_pv_SHIFT 19 2533 #define wqe_pv_MASK 0x00000001 2534 #define wqe_pv_WORD word10 2535 #define wqe_xc_SHIFT 21 2536 #define wqe_xc_MASK 0x00000001 2537 #define wqe_xc_WORD word10 2538 #define wqe_ccpe_SHIFT 23 2539 #define wqe_ccpe_MASK 0x00000001 2540 #define wqe_ccpe_WORD word10 2541 #define wqe_ccp_SHIFT 24 2542 #define wqe_ccp_MASK 0x000000ff 2543 #define wqe_ccp_WORD word10 2544 uint32_t word11; 2545 #define wqe_cmd_type_SHIFT 0 2546 #define wqe_cmd_type_MASK 0x0000000f 2547 #define wqe_cmd_type_WORD word11 2548 #define wqe_els_id_SHIFT 4 2549 #define wqe_els_id_MASK 0x00000003 2550 #define wqe_els_id_WORD word11 2551 #define LPFC_ELS_ID_FLOGI 3 2552 #define LPFC_ELS_ID_FDISC 2 2553 #define LPFC_ELS_ID_LOGO 1 2554 #define LPFC_ELS_ID_DEFAULT 0 2555 #define wqe_wqec_SHIFT 7 2556 #define wqe_wqec_MASK 0x00000001 2557 #define wqe_wqec_WORD word11 2558 #define wqe_cqid_SHIFT 16 2559 #define wqe_cqid_MASK 0x0000ffff 2560 #define wqe_cqid_WORD word11 2561 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 2562 }; 2563 2564 struct wqe_did { 2565 uint32_t word5; 2566 #define wqe_els_did_SHIFT 0 2567 #define wqe_els_did_MASK 0x00FFFFFF 2568 #define wqe_els_did_WORD word5 2569 #define wqe_xmit_bls_pt_SHIFT 28 2570 #define wqe_xmit_bls_pt_MASK 0x00000003 2571 #define wqe_xmit_bls_pt_WORD word5 2572 #define wqe_xmit_bls_ar_SHIFT 30 2573 #define wqe_xmit_bls_ar_MASK 0x00000001 2574 #define wqe_xmit_bls_ar_WORD word5 2575 #define wqe_xmit_bls_xo_SHIFT 31 2576 #define wqe_xmit_bls_xo_MASK 0x00000001 2577 #define wqe_xmit_bls_xo_WORD word5 2578 }; 2579 2580 struct lpfc_wqe_generic{ 2581 struct ulp_bde64 bde; 2582 uint32_t word3; 2583 uint32_t word4; 2584 uint32_t word5; 2585 struct wqe_common wqe_com; 2586 uint32_t payload[4]; 2587 }; 2588 2589 struct els_request64_wqe { 2590 struct ulp_bde64 bde; 2591 uint32_t payload_len; 2592 uint32_t word4; 2593 #define els_req64_sid_SHIFT 0 2594 #define els_req64_sid_MASK 0x00FFFFFF 2595 #define els_req64_sid_WORD word4 2596 #define els_req64_sp_SHIFT 24 2597 #define els_req64_sp_MASK 0x00000001 2598 #define els_req64_sp_WORD word4 2599 #define els_req64_vf_SHIFT 25 2600 #define els_req64_vf_MASK 0x00000001 2601 #define els_req64_vf_WORD word4 2602 struct wqe_did wqe_dest; 2603 struct wqe_common wqe_com; /* words 6-11 */ 2604 uint32_t word12; 2605 #define els_req64_vfid_SHIFT 1 2606 #define els_req64_vfid_MASK 0x00000FFF 2607 #define els_req64_vfid_WORD word12 2608 #define els_req64_pri_SHIFT 13 2609 #define els_req64_pri_MASK 0x00000007 2610 #define els_req64_pri_WORD word12 2611 uint32_t word13; 2612 #define els_req64_hopcnt_SHIFT 24 2613 #define els_req64_hopcnt_MASK 0x000000ff 2614 #define els_req64_hopcnt_WORD word13 2615 uint32_t reserved[2]; 2616 }; 2617 2618 struct xmit_els_rsp64_wqe { 2619 struct ulp_bde64 bde; 2620 uint32_t response_payload_len; 2621 uint32_t rsvd4; 2622 struct wqe_did wqe_dest; 2623 struct wqe_common wqe_com; /* words 6-11 */ 2624 uint32_t rsvd_12_15[4]; 2625 }; 2626 2627 struct xmit_bls_rsp64_wqe { 2628 uint32_t payload0; 2629 /* Payload0 for BA_ACC */ 2630 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 2631 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 2632 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 2633 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 2634 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 2635 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 2636 /* Payload0 for BA_RJT */ 2637 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 2638 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 2639 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 2640 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 2641 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 2642 #define xmit_bls_rsp64_rjt_expc_WORD payload0 2643 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 2644 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 2645 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 2646 uint32_t word1; 2647 #define xmit_bls_rsp64_rxid_SHIFT 0 2648 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 2649 #define xmit_bls_rsp64_rxid_WORD word1 2650 #define xmit_bls_rsp64_oxid_SHIFT 16 2651 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 2652 #define xmit_bls_rsp64_oxid_WORD word1 2653 uint32_t word2; 2654 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 2655 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 2656 #define xmit_bls_rsp64_seqcnthi_WORD word2 2657 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 2658 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 2659 #define xmit_bls_rsp64_seqcntlo_WORD word2 2660 uint32_t rsrvd3; 2661 uint32_t rsrvd4; 2662 struct wqe_did wqe_dest; 2663 struct wqe_common wqe_com; /* words 6-11 */ 2664 uint32_t rsvd_12_15[4]; 2665 }; 2666 2667 struct wqe_rctl_dfctl { 2668 uint32_t word5; 2669 #define wqe_si_SHIFT 2 2670 #define wqe_si_MASK 0x000000001 2671 #define wqe_si_WORD word5 2672 #define wqe_la_SHIFT 3 2673 #define wqe_la_MASK 0x000000001 2674 #define wqe_la_WORD word5 2675 #define wqe_ls_SHIFT 7 2676 #define wqe_ls_MASK 0x000000001 2677 #define wqe_ls_WORD word5 2678 #define wqe_dfctl_SHIFT 8 2679 #define wqe_dfctl_MASK 0x0000000ff 2680 #define wqe_dfctl_WORD word5 2681 #define wqe_type_SHIFT 16 2682 #define wqe_type_MASK 0x0000000ff 2683 #define wqe_type_WORD word5 2684 #define wqe_rctl_SHIFT 24 2685 #define wqe_rctl_MASK 0x0000000ff 2686 #define wqe_rctl_WORD word5 2687 }; 2688 2689 struct xmit_seq64_wqe { 2690 struct ulp_bde64 bde; 2691 uint32_t rsvd3; 2692 uint32_t relative_offset; 2693 struct wqe_rctl_dfctl wge_ctl; 2694 struct wqe_common wqe_com; /* words 6-11 */ 2695 uint32_t xmit_len; 2696 uint32_t rsvd_12_15[3]; 2697 }; 2698 struct xmit_bcast64_wqe { 2699 struct ulp_bde64 bde; 2700 uint32_t seq_payload_len; 2701 uint32_t rsvd4; 2702 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 2703 struct wqe_common wqe_com; /* words 6-11 */ 2704 uint32_t rsvd_12_15[4]; 2705 }; 2706 2707 struct gen_req64_wqe { 2708 struct ulp_bde64 bde; 2709 uint32_t request_payload_len; 2710 uint32_t relative_offset; 2711 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 2712 struct wqe_common wqe_com; /* words 6-11 */ 2713 uint32_t rsvd_12_15[4]; 2714 }; 2715 2716 struct create_xri_wqe { 2717 uint32_t rsrvd[5]; /* words 0-4 */ 2718 struct wqe_did wqe_dest; /* word 5 */ 2719 struct wqe_common wqe_com; /* words 6-11 */ 2720 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2721 }; 2722 2723 #define T_REQUEST_TAG 3 2724 #define T_XRI_TAG 1 2725 2726 struct abort_cmd_wqe { 2727 uint32_t rsrvd[3]; 2728 uint32_t word3; 2729 #define abort_cmd_ia_SHIFT 0 2730 #define abort_cmd_ia_MASK 0x000000001 2731 #define abort_cmd_ia_WORD word3 2732 #define abort_cmd_criteria_SHIFT 8 2733 #define abort_cmd_criteria_MASK 0x0000000ff 2734 #define abort_cmd_criteria_WORD word3 2735 uint32_t rsrvd4; 2736 uint32_t rsrvd5; 2737 struct wqe_common wqe_com; /* words 6-11 */ 2738 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2739 }; 2740 2741 struct fcp_iwrite64_wqe { 2742 struct ulp_bde64 bde; 2743 uint32_t payload_offset_len; 2744 uint32_t total_xfer_len; 2745 uint32_t initial_xfer_len; 2746 struct wqe_common wqe_com; /* words 6-11 */ 2747 uint32_t rsrvd12; 2748 struct ulp_bde64 ph_bde; /* words 13-15 */ 2749 }; 2750 2751 struct fcp_iread64_wqe { 2752 struct ulp_bde64 bde; 2753 uint32_t payload_offset_len; /* word 3 */ 2754 uint32_t total_xfer_len; /* word 4 */ 2755 uint32_t rsrvd5; /* word 5 */ 2756 struct wqe_common wqe_com; /* words 6-11 */ 2757 uint32_t rsrvd12; 2758 struct ulp_bde64 ph_bde; /* words 13-15 */ 2759 }; 2760 2761 struct fcp_icmnd64_wqe { 2762 struct ulp_bde64 bde; /* words 0-2 */ 2763 uint32_t rsrvd3; /* word 3 */ 2764 uint32_t rsrvd4; /* word 4 */ 2765 uint32_t rsrvd5; /* word 5 */ 2766 struct wqe_common wqe_com; /* words 6-11 */ 2767 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2768 }; 2769 2770 2771 union lpfc_wqe { 2772 uint32_t words[16]; 2773 struct lpfc_wqe_generic generic; 2774 struct fcp_icmnd64_wqe fcp_icmd; 2775 struct fcp_iread64_wqe fcp_iread; 2776 struct fcp_iwrite64_wqe fcp_iwrite; 2777 struct abort_cmd_wqe abort_cmd; 2778 struct create_xri_wqe create_xri; 2779 struct xmit_bcast64_wqe xmit_bcast64; 2780 struct xmit_seq64_wqe xmit_sequence; 2781 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 2782 struct xmit_els_rsp64_wqe xmit_els_rsp; 2783 struct els_request64_wqe els_req; 2784 struct gen_req64_wqe gen_req; 2785 }; 2786 2787 #define FCP_COMMAND 0x0 2788 #define FCP_COMMAND_DATA_OUT 0x1 2789 #define ELS_COMMAND_NON_FIP 0xC 2790 #define ELS_COMMAND_FIP 0xD 2791 #define OTHER_COMMAND 0x8 2792 2793