1 /* 2 * Copyright 2005-2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later. 5 */ 6 7 #ifndef _BF561_IRQ_H_ 8 #define _BF561_IRQ_H_ 9 10 /*********************************************************************** 11 * Interrupt source definitions: 12 Event Source Core Event Name IRQ No 13 (highest priority) 14 Emulation Events EMU 0 15 Reset RST 1 16 NMI NMI 2 17 Exception EVX 3 18 Reserved -- 4 19 Hardware Error IVHW 5 20 Core Timer IVTMR 6 * 21 22 PLL Wakeup Interrupt IVG7 7 23 DMA1 Error (generic) IVG7 8 24 DMA2 Error (generic) IVG7 9 25 IMDMA Error (generic) IVG7 10 26 PPI1 Error Interrupt IVG7 11 27 PPI2 Error Interrupt IVG7 12 28 SPORT0 Error Interrupt IVG7 13 29 SPORT1 Error Interrupt IVG7 14 30 SPI Error Interrupt IVG7 15 31 UART Error Interrupt IVG7 16 32 Reserved Interrupt IVG7 17 33 34 DMA1 0 Interrupt(PPI1) IVG8 18 35 DMA1 1 Interrupt(PPI2) IVG8 19 36 DMA1 2 Interrupt IVG8 20 37 DMA1 3 Interrupt IVG8 21 38 DMA1 4 Interrupt IVG8 22 39 DMA1 5 Interrupt IVG8 23 40 DMA1 6 Interrupt IVG8 24 41 DMA1 7 Interrupt IVG8 25 42 DMA1 8 Interrupt IVG8 26 43 DMA1 9 Interrupt IVG8 27 44 DMA1 10 Interrupt IVG8 28 45 DMA1 11 Interrupt IVG8 29 46 47 DMA2 0 (SPORT0 RX) IVG9 30 48 DMA2 1 (SPORT0 TX) IVG9 31 49 DMA2 2 (SPORT1 RX) IVG9 32 50 DMA2 3 (SPORT2 TX) IVG9 33 51 DMA2 4 (SPI) IVG9 34 52 DMA2 5 (UART RX) IVG9 35 53 DMA2 6 (UART TX) IVG9 36 54 DMA2 7 Interrupt IVG9 37 55 DMA2 8 Interrupt IVG9 38 56 DMA2 9 Interrupt IVG9 39 57 DMA2 10 Interrupt IVG9 40 58 DMA2 11 Interrupt IVG9 41 59 60 TIMER 0 Interrupt IVG10 42 61 TIMER 1 Interrupt IVG10 43 62 TIMER 2 Interrupt IVG10 44 63 TIMER 3 Interrupt IVG10 45 64 TIMER 4 Interrupt IVG10 46 65 TIMER 5 Interrupt IVG10 47 66 TIMER 6 Interrupt IVG10 48 67 TIMER 7 Interrupt IVG10 49 68 TIMER 8 Interrupt IVG10 50 69 TIMER 9 Interrupt IVG10 51 70 TIMER 10 Interrupt IVG10 52 71 TIMER 11 Interrupt IVG10 53 72 73 Programmable Flags0 A (8) IVG11 54 74 Programmable Flags0 B (8) IVG11 55 75 Programmable Flags1 A (8) IVG11 56 76 Programmable Flags1 B (8) IVG11 57 77 Programmable Flags2 A (8) IVG11 58 78 Programmable Flags2 B (8) IVG11 59 79 80 MDMA1 0 write/read INT IVG8 60 81 MDMA1 1 write/read INT IVG8 61 82 83 MDMA2 0 write/read INT IVG9 62 84 MDMA2 1 write/read INT IVG9 63 85 86 IMDMA 0 write/read INT IVG12 64 87 IMDMA 1 write/read INT IVG12 65 88 89 Watch Dog Timer IVG13 66 90 91 Reserved interrupt IVG7 67 92 Reserved interrupt IVG7 68 93 Supplemental interrupt 0 IVG7 69 94 supplemental interrupt 1 IVG7 70 95 96 Softirq IVG14 97 System Call -- 98 (lowest priority) IVG15 99 100 **********************************************************************/ 101 102 #define SYS_IRQS 71 103 #define NR_PERI_INTS 64 104 105 /* 106 * The ABSTRACT IRQ definitions 107 * the first seven of the following are fixed, 108 * the rest you change if you need to. 109 */ 110 /* IVG 0-6*/ 111 #define IRQ_EMU 0 /* Emulation */ 112 #define IRQ_RST 1 /* Reset */ 113 #define IRQ_NMI 2 /* Non Maskable Interrupt */ 114 #define IRQ_EVX 3 /* Exception */ 115 #define IRQ_UNUSED 4 /* Reserved interrupt */ 116 #define IRQ_HWERR 5 /* Hardware Error */ 117 #define IRQ_CORETMR 6 /* Core timer */ 118 119 #define IVG_BASE 7 120 /* IVG 7 */ 121 #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ 122 #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ 123 #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ 124 #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ 125 #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ 126 #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ 127 #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ 128 #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ 129 #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ 130 #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ 131 #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ 132 #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ 133 #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */ 134 /* IVG 8 */ 135 #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ 136 #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ 137 #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ 138 #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ 139 #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ 140 #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ 141 #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ 142 #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ 143 #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ 144 #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ 145 #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ 146 #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ 147 #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ 148 #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ 149 #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ 150 /* IVG 9 */ 151 #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ 152 #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ 153 #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ 154 #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ 155 #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ 156 #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ 157 #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ 158 #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ 159 #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ 160 #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ 161 #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ 162 #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ 163 #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ 164 #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ 165 #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ 166 #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ 167 #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ 168 #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ 169 #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ 170 /* IVG 10 */ 171 #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ 172 #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ 173 #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ 174 #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ 175 #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ 176 #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ 177 #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ 178 #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ 179 #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ 180 #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ 181 #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ 182 #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ 183 /* IVG 11 */ 184 #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ 185 #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ 186 #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ 187 #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ 188 #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ 189 #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ 190 #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ 191 #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ 192 /* IVG 8 */ 193 #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ 194 #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ 195 #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 196 #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ 197 #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ 198 #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 199 /* IVG 9 */ 200 #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ 201 #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 202 #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ 203 #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 204 /* IVG 12 */ 205 #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ 206 #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 207 #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ 208 #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 209 /* IVG 13 */ 210 #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ 211 /* IVG 7 */ 212 #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ 213 #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ 214 #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 215 #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 216 217 #define IRQ_PF0 73 218 #define IRQ_PF1 74 219 #define IRQ_PF2 75 220 #define IRQ_PF3 76 221 #define IRQ_PF4 77 222 #define IRQ_PF5 78 223 #define IRQ_PF6 79 224 #define IRQ_PF7 80 225 #define IRQ_PF8 81 226 #define IRQ_PF9 82 227 #define IRQ_PF10 83 228 #define IRQ_PF11 84 229 #define IRQ_PF12 85 230 #define IRQ_PF13 86 231 #define IRQ_PF14 87 232 #define IRQ_PF15 88 233 #define IRQ_PF16 89 234 #define IRQ_PF17 90 235 #define IRQ_PF18 91 236 #define IRQ_PF19 92 237 #define IRQ_PF20 93 238 #define IRQ_PF21 94 239 #define IRQ_PF22 95 240 #define IRQ_PF23 96 241 #define IRQ_PF24 97 242 #define IRQ_PF25 98 243 #define IRQ_PF26 99 244 #define IRQ_PF27 100 245 #define IRQ_PF28 101 246 #define IRQ_PF29 102 247 #define IRQ_PF30 103 248 #define IRQ_PF31 104 249 #define IRQ_PF32 105 250 #define IRQ_PF33 106 251 #define IRQ_PF34 107 252 #define IRQ_PF35 108 253 #define IRQ_PF36 109 254 #define IRQ_PF37 110 255 #define IRQ_PF38 111 256 #define IRQ_PF39 112 257 #define IRQ_PF40 113 258 #define IRQ_PF41 114 259 #define IRQ_PF42 115 260 #define IRQ_PF43 116 261 #define IRQ_PF44 117 262 #define IRQ_PF45 118 263 #define IRQ_PF46 119 264 #define IRQ_PF47 120 265 266 #define GPIO_IRQ_BASE IRQ_PF0 267 268 #define NR_MACH_IRQS (IRQ_PF47 + 1) 269 #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 270 271 #define IVG7 7 272 #define IVG8 8 273 #define IVG9 9 274 #define IVG10 10 275 #define IVG11 11 276 #define IVG12 12 277 #define IVG13 13 278 #define IVG14 14 279 #define IVG15 15 280 281 /* 282 * DEFAULT PRIORITIES: 283 */ 284 285 #define CONFIG_DEF_PLL_WAKEUP 7 286 #define CONFIG_DEF_DMA1_ERROR 7 287 #define CONFIG_DEF_DMA2_ERROR 7 288 #define CONFIG_DEF_IMDMA_ERROR 7 289 #define CONFIG_DEF_PPI1_ERROR 7 290 #define CONFIG_DEF_PPI2_ERROR 7 291 #define CONFIG_DEF_SPORT0_ERROR 7 292 #define CONFIG_DEF_SPORT1_ERROR 7 293 #define CONFIG_DEF_SPI_ERROR 7 294 #define CONFIG_DEF_UART_ERROR 7 295 #define CONFIG_DEF_RESERVED_ERROR 7 296 #define CONFIG_DEF_DMA1_0 8 297 #define CONFIG_DEF_DMA1_1 8 298 #define CONFIG_DEF_DMA1_2 8 299 #define CONFIG_DEF_DMA1_3 8 300 #define CONFIG_DEF_DMA1_4 8 301 #define CONFIG_DEF_DMA1_5 8 302 #define CONFIG_DEF_DMA1_6 8 303 #define CONFIG_DEF_DMA1_7 8 304 #define CONFIG_DEF_DMA1_8 8 305 #define CONFIG_DEF_DMA1_9 8 306 #define CONFIG_DEF_DMA1_10 8 307 #define CONFIG_DEF_DMA1_11 8 308 #define CONFIG_DEF_DMA2_0 9 309 #define CONFIG_DEF_DMA2_1 9 310 #define CONFIG_DEF_DMA2_2 9 311 #define CONFIG_DEF_DMA2_3 9 312 #define CONFIG_DEF_DMA2_4 9 313 #define CONFIG_DEF_DMA2_5 9 314 #define CONFIG_DEF_DMA2_6 9 315 #define CONFIG_DEF_DMA2_7 9 316 #define CONFIG_DEF_DMA2_8 9 317 #define CONFIG_DEF_DMA2_9 9 318 #define CONFIG_DEF_DMA2_10 9 319 #define CONFIG_DEF_DMA2_11 9 320 #define CONFIG_DEF_TIMER0 10 321 #define CONFIG_DEF_TIMER1 10 322 #define CONFIG_DEF_TIMER2 10 323 #define CONFIG_DEF_TIMER3 10 324 #define CONFIG_DEF_TIMER4 10 325 #define CONFIG_DEF_TIMER5 10 326 #define CONFIG_DEF_TIMER6 10 327 #define CONFIG_DEF_TIMER7 10 328 #define CONFIG_DEF_TIMER8 10 329 #define CONFIG_DEF_TIMER9 10 330 #define CONFIG_DEF_TIMER10 10 331 #define CONFIG_DEF_TIMER11 10 332 #define CONFIG_DEF_PROG0_INTA 11 333 #define CONFIG_DEF_PROG0_INTB 11 334 #define CONFIG_DEF_PROG1_INTA 11 335 #define CONFIG_DEF_PROG1_INTB 11 336 #define CONFIG_DEF_PROG2_INTA 11 337 #define CONFIG_DEF_PROG2_INTB 11 338 #define CONFIG_DEF_DMA1_WRRD0 8 339 #define CONFIG_DEF_DMA1_WRRD1 8 340 #define CONFIG_DEF_DMA2_WRRD0 9 341 #define CONFIG_DEF_DMA2_WRRD1 9 342 #define CONFIG_DEF_IMDMA_WRRD0 12 343 #define CONFIG_DEF_IMDMA_WRRD1 12 344 #define CONFIG_DEF_WATCH 13 345 #define CONFIG_DEF_RESERVED_1 7 346 #define CONFIG_DEF_RESERVED_2 7 347 #define CONFIG_DEF_SUPPLE_0 7 348 #define CONFIG_DEF_SUPPLE_1 7 349 350 /* IAR0 BIT FIELDS */ 351 #define IRQ_PLL_WAKEUP_POS 0 352 #define IRQ_DMA1_ERROR_POS 4 353 #define IRQ_DMA2_ERROR_POS 8 354 #define IRQ_IMDMA_ERROR_POS 12 355 #define IRQ_PPI0_ERROR_POS 16 356 #define IRQ_PPI1_ERROR_POS 20 357 #define IRQ_SPORT0_ERROR_POS 24 358 #define IRQ_SPORT1_ERROR_POS 28 359 /* IAR1 BIT FIELDS */ 360 #define IRQ_SPI_ERROR_POS 0 361 #define IRQ_UART_ERROR_POS 4 362 #define IRQ_RESERVED_ERROR_POS 8 363 #define IRQ_DMA1_0_POS 12 364 #define IRQ_DMA1_1_POS 16 365 #define IRQ_DMA1_2_POS 20 366 #define IRQ_DMA1_3_POS 24 367 #define IRQ_DMA1_4_POS 28 368 /* IAR2 BIT FIELDS */ 369 #define IRQ_DMA1_5_POS 0 370 #define IRQ_DMA1_6_POS 4 371 #define IRQ_DMA1_7_POS 8 372 #define IRQ_DMA1_8_POS 12 373 #define IRQ_DMA1_9_POS 16 374 #define IRQ_DMA1_10_POS 20 375 #define IRQ_DMA1_11_POS 24 376 #define IRQ_DMA2_0_POS 28 377 /* IAR3 BIT FIELDS */ 378 #define IRQ_DMA2_1_POS 0 379 #define IRQ_DMA2_2_POS 4 380 #define IRQ_DMA2_3_POS 8 381 #define IRQ_DMA2_4_POS 12 382 #define IRQ_DMA2_5_POS 16 383 #define IRQ_DMA2_6_POS 20 384 #define IRQ_DMA2_7_POS 24 385 #define IRQ_DMA2_8_POS 28 386 /* IAR4 BIT FIELDS */ 387 #define IRQ_DMA2_9_POS 0 388 #define IRQ_DMA2_10_POS 4 389 #define IRQ_DMA2_11_POS 8 390 #define IRQ_TIMER0_POS 12 391 #define IRQ_TIMER1_POS 16 392 #define IRQ_TIMER2_POS 20 393 #define IRQ_TIMER3_POS 24 394 #define IRQ_TIMER4_POS 28 395 /* IAR5 BIT FIELDS */ 396 #define IRQ_TIMER5_POS 0 397 #define IRQ_TIMER6_POS 4 398 #define IRQ_TIMER7_POS 8 399 #define IRQ_TIMER8_POS 12 400 #define IRQ_TIMER9_POS 16 401 #define IRQ_TIMER10_POS 20 402 #define IRQ_TIMER11_POS 24 403 #define IRQ_PROG0_INTA_POS 28 404 /* IAR6 BIT FIELDS */ 405 #define IRQ_PROG0_INTB_POS 0 406 #define IRQ_PROG1_INTA_POS 4 407 #define IRQ_PROG1_INTB_POS 8 408 #define IRQ_PROG2_INTA_POS 12 409 #define IRQ_PROG2_INTB_POS 16 410 #define IRQ_DMA1_WRRD0_POS 20 411 #define IRQ_DMA1_WRRD1_POS 24 412 #define IRQ_DMA2_WRRD0_POS 28 413 /* IAR7 BIT FIELDS */ 414 #define IRQ_DMA2_WRRD1_POS 0 415 #define IRQ_IMDMA_WRRD0_POS 4 416 #define IRQ_IMDMA_WRRD1_POS 8 417 #define IRQ_WDTIMER_POS 12 418 #define IRQ_RESERVED_1_POS 16 419 #define IRQ_RESERVED_2_POS 20 420 #define IRQ_SUPPLE_0_POS 24 421 #define IRQ_SUPPLE_1_POS 28 422 423 #endif /* _BF561_IRQ_H_ */ 424