Home
last modified time | relevance | path

Searched refs:IOMEM (Results 1 – 25 of 34) sorted by relevance

12

/linux-2.6.39/arch/arm/plat-omap/include/plat/
Dfpga.h38 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
39 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
40 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
41 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
42 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
43 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
44 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
89 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
90 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
92 #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
[all …]
Dio.h58 #define IOMEM(x) (x)
60 #define IOMEM(x) ((void __force __iomem *)(x)) macro
64 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
67 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
71 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
74 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
77 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
80 #define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
83 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
Dhardware.h92 #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
/linux-2.6.39/arch/arm/mach-msm/include/mach/
Dmsm_iomap-7x30.h38 #define MSM_VIC_BASE IOMEM(0xE0000000)
45 #define MSM_DMOV_BASE IOMEM(0xE0002000)
49 #define MSM_GPIO1_BASE IOMEM(0xE0003000)
53 #define MSM_GPIO2_BASE IOMEM(0xE0004000)
57 #define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
61 #define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
65 #define MSM_ACC_BASE IOMEM(0xE0007000)
69 #define MSM_SAW_BASE IOMEM(0xE0008000)
73 #define MSM_GCC_BASE IOMEM(0xE0009000)
77 #define MSM_TCSR_BASE IOMEM(0xE000A000)
[all …]
Dmsm_iomap-8x50.h38 #define MSM_VIC_BASE IOMEM(0xE0000000)
45 #define MSM_DMOV_BASE IOMEM(0xE0002000)
49 #define MSM_GPIO1_BASE IOMEM(0xE0003000)
53 #define MSM_GPIO2_BASE IOMEM(0xE0004000)
57 #define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
61 #define MSM_SIRC_BASE IOMEM(0xE1006000)
65 #define MSM_SCPLL_BASE IOMEM(0xE1007000)
75 #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
100 #define MSM_MDC_BASE IOMEM(0xE0200000)
104 #define MSM_AD5_BASE IOMEM(0xE0300000)
Dmsm_iomap.h41 #define IOMEM(x) x
43 #define IOMEM(x) ((void __force __iomem *)(x)) macro
59 #define MSM_CSR_BASE IOMEM(0xE0001000)
60 #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
61 #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
62 #define MSM_TMR_BASE IOMEM(0xF0200000)
63 #define MSM_TMR0_BASE IOMEM(0xF0201000)
Dmsm_iomap-7x00.h42 #define IOMEM(x) x
44 #define IOMEM(x) ((void __force __iomem *)(x)) macro
47 #define MSM_VIC_BASE IOMEM(0xE0000000)
54 #define MSM_DMOV_BASE IOMEM(0xE0002000)
58 #define MSM_GPIO1_BASE IOMEM(0xE0003000)
62 #define MSM_GPIO2_BASE IOMEM(0xE0004000)
66 #define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
70 #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
Dmsm_iomap-8x60.h44 #define MSM_ACC_BASE IOMEM(0xF0002000)
48 #define MSM_GCC_BASE IOMEM(0xF0003000)
52 #define MSM_TLMM_BASE IOMEM(0xF0004000)
56 #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
/linux-2.6.39/arch/arm/mach-rpc/include/mach/
Dhardware.h18 #define IOMEM(x) ((void __iomem *)(unsigned long)(x)) macro
20 #define IOMEM(x) x macro
43 #define IO_BASE IOMEM(0xe0000000)
54 #define VIDC_BASE IOMEM(0xe0400000)
56 #define IOMD_BASE IOMEM(0xe0200000)
57 #define IOC_BASE IOMEM(0xe0200000)
58 #define PCIO_BASE IOMEM(0xe0010000)
59 #define FLOPPYDMA_BASE IOMEM(0xe002a000)
/linux-2.6.39/arch/arm/mach-davinci/include/mach/
Dhardware.h36 #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
39 #define IOMEM(x) x
41 #define IOMEM(x) ((void __force __iomem *)(x)) macro
Dserial.h39 #define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
40 #define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
41 #define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
/linux-2.6.39/arch/arm/plat-mxc/include/mach/
Dhardware.h26 #define IOMEM(addr) (addr)
28 #define IOMEM(addr) ((void __force __iomem *)(addr)) macro
105 #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
Dmx25.h61 #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
Dmx1.h80 #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
Dmx21.h99 #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
Dmx35.h118 #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
/linux-2.6.39/arch/arm/plat-spear/include/plat/
Dhardware.h18 #define IOMEM(x) ((void __iomem __force *)(x)) macro
20 #define IOMEM(x) (x) macro
/linux-2.6.39/arch/arm/mach-mxs/include/mach/
Dhardware.h24 #define IOMEM(addr) (addr)
26 #define IOMEM(addr) ((void __force __iomem *)(addr)) macro
Dmxs.h80 #define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
Dmx23.h72 #define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x))
Dmx28.h91 #define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
/linux-2.6.39/arch/arm/mach-ep93xx/include/mach/
Dio.h17 #define IOMEM(p) p
19 #define IOMEM(p) ((void __iomem __force *)(p)) macro
Dep93xx-regs.h56 #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
63 #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
/linux-2.6.39/arch/arm/mach-spear3xx/include/mach/
Dmisc_regs.h19 #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
/linux-2.6.39/arch/arm/mach-spear6xx/include/mach/
Dmisc_regs.h19 #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)

12