Searched refs:HSYNC (Results 1 – 9 of 9) sorted by relevance
| /linux-2.6.39/drivers/video/i810/ |
| D | i810_regs.h | 150 #define HSYNC 0x60008 macro
|
| /linux-2.6.39/Documentation/fb/ |
| D | pxafb.txt | 27 hsynclen:HSYNC == LCCR1_HSW + 1
45 hsync:HSYNC
|
| D | matroxfb.txt | 250 left:X - left boundary: pixels between end of HSYNC pulse and first pixel.
252 right:X - right boundary: pixels between end of picture and start of HSYNC
254 hslen:X - length of HSYNC pulse, in pixels. Default is derived from `vesa'
258 sync:X - sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
259 If bit 3 (value 0x08) is set, composite sync instead of HSYNC is
|
| /linux-2.6.39/include/video/ |
| D | sstfb.h | 160 #define HSYNC 0x0220 macro
|
| /linux-2.6.39/arch/avr32/mach-at32ap/include/mach/ |
| D | at32ap700x.h | 227 ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) | \
|
| /linux-2.6.39/drivers/gpu/drm/i2c/ |
| D | ch7006_mode.c | 122 .flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
|
| /linux-2.6.39/drivers/video/ |
| D | sstfb.c | 533 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); in sstfb_set_par()
|
| /linux-2.6.39/drivers/gpu/drm/i915/ |
| D | intel_display.c | 2781 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); in ironlake_pch_enable()
5105 I915_WRITE(HSYNC(pipe), in intel_crtc_mode_set()
5693 int hsync = I915_READ(HSYNC(pipe)); in intel_crtc_mode_get()
7616 error->pipe[i].hsync = I915_READ(HSYNC(i)); in intel_display_capture_error_state()
|
| D | i915_reg.h | 1295 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) macro
|