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Searched refs:GxICR (Results 1 – 14 of 14) sorted by relevance

/linux-2.6.39/arch/mn10300/include/asm/
Dtimer-regs.h106 #define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
107 #define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
108 #define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
109 #define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
325 #define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
326 #define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
327 #define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
328 #define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
329 #define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
330 #define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
[all …]
Dserial-regs.h92 #define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
93 #define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
105 #define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
106 #define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
185 #define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
186 #define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
Dintctl-regs.h22 #define GxICR(X) \ macro
39 #define NMICR GxICR(NMIIRQ) /* NMI control register */
67 #define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
Dtimex.h39 GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; in setup_jiffies_interrupt()
40 tmp = GxICR(irq); in setup_jiffies_interrupt()
Drtc-regs.h70 #define RTICR GxICR(RTIRQ)
/linux-2.6.39/arch/mn10300/kernel/
Dirq.c48 tmp = GxICR(irq); in mn10300_cpupic_ack()
59 tmp = GxICR(irq); in __mask_and_set_icr()
60 GxICR(irq) = (tmp & mask) | set; in __mask_and_set_icr()
61 tmp = GxICR(irq); in __mask_and_set_icr()
80 tmp = GxICR(irq); in mn10300_cpupic_mask_ack()
81 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; in mn10300_cpupic_mask_ack()
82 tmp = GxICR(irq); in mn10300_cpupic_mask_ack()
85 tmp = GxICR(irq); in mn10300_cpupic_mask_ack()
86 GxICR(irq) = (tmp & GxICR_LEVEL); in mn10300_cpupic_mask_ack()
87 tmp2 = GxICR(irq); in mn10300_cpupic_mask_ack()
[all …]
Dsmp.c187 GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT; in init_ipi()
194 GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT; in init_ipi()
195 tmp16 = GxICR(CALL_FUNCTION_NMI_IPI); in init_ipi()
216 tmp = GxICR(irq); in mn10300_ipi_shutdown()
217 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT; in mn10300_ipi_shutdown()
218 tmp = GxICR(irq); in mn10300_ipi_shutdown()
234 tmp = GxICR(irq); in mn10300_ipi_enable()
235 GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE; in mn10300_ipi_enable()
236 tmp = GxICR(irq); in mn10300_ipi_enable()
257 tmp = GxICR(irq); in mn10300_ipi_disable()
[all …]
Dsmp-low.S66 movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt
67 movhu (GxICR(FLUSH_CACHE_IPI)),d2
80 movhu (GxICR(SMP_BOOT_IRQ)),d0
82 movhu d0,(GxICR(SMP_BOOT_IRQ))
Dgdb-io-ttysm-low.S57 movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt
58 movhu (GxICR(SCgRXIRQ)),d2 # flush
Dmn10300-serial.c48 #undef GxICR
49 #define GxICR(X) CROSS_GxICR(X, 0) macro
205 .rx_icr = &GxICR(SC0RXIRQ),
206 .tx_icr = &GxICR(SC0TXIRQ),
267 .rx_icr = &GxICR(SC1RXIRQ),
268 .tx_icr = &GxICR(SC1TXIRQ),
340 .rx_icr = &GxICR(SC2RXIRQ),
341 .tx_icr = &GxICR(SC2TXIRQ),
390 GxICR(irq) = GxICR_LEVEL_6; in mn10300_serial_mask_ack()
391 tmp = GxICR(irq); /* flush write buffer */ in mn10300_serial_mask_ack()
/linux-2.6.39/arch/mn10300/proc-mn103e010/include/proc/
Ddmactl-regs.h83 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
84 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
85 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
86 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-2.6.39/arch/mn10300/proc-mn2ws0050/include/proc/
Ddmactl-regs.h84 #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
85 #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
86 #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
87 #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
/linux-2.6.39/arch/mn10300/proc-mn2ws0050/
Dproc-init.c77 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; in processor_init()
80 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; in processor_init()
/linux-2.6.39/arch/mn10300/proc-mn103e010/
Dproc-init.c59 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; in processor_init()