Searched refs:EVERGREEN_CRTC1_REGISTER_OFFSET (Results 1 – 5 of 5) sorted by relevance
970 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_mc_stop()981 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); in evergreen_mc_stop()989 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_mc_stop()997 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_mc_stop()1024 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_mc_resume()1026 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_mc_resume()1028 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_mc_resume()1030 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_mc_resume()1084 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); in evergreen_mc_resume()1092 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); in evergreen_mc_resume()[all …]
173 #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) macro
350 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_card_posted()355 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | in radeon_card_posted()
1520 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()1522 EVERGREEN_CRTC1_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1557 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()