1 /*
2 * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
3 * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
4 * like hx4700).
5 *
6 * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
7 * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
8 *
9 * Use consistent with the GNU GPL is permitted,
10 * provided that this copyright notice is
11 * preserved in its entirety in all copies and derived works.
12 */
13
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/pm.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/mfd/core.h>
22 #include <linux/mfd/ds1wm.h>
23 #include <linux/slab.h>
24
25 #include <asm/io.h>
26
27 #include "../w1.h"
28 #include "../w1_int.h"
29
30
31 #define DS1WM_CMD 0x00 /* R/W 4 bits command */
32 #define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */
33 #define DS1WM_INT 0x02 /* R/W interrupt status */
34 #define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
35 #define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
36
37 #define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
38 #define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
39 #define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */
40 #define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */
41 #define DS1WM_CMD_RST (1 << 5) /* software reset */
42 #define DS1WM_CMD_OD (1 << 7) /* overdrive */
43
44 #define DS1WM_INT_PD (1 << 0) /* presence detect */
45 #define DS1WM_INT_PDR (1 << 1) /* presence detect result */
46 #define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */
47 #define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */
48 #define DS1WM_INT_RBF (1 << 4) /* rx buffer full */
49 #define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */
50
51 #define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */
52 #define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */
53 #define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */
54 #define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */
55 #define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */
56 #define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
57 #define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
58
59
60 #define DS1WM_TIMEOUT (HZ * 5)
61
62 static struct {
63 unsigned long freq;
64 unsigned long divisor;
65 } freq[] = {
66 { 4000000, 0x8 },
67 { 5000000, 0x2 },
68 { 6000000, 0x5 },
69 { 7000000, 0x3 },
70 { 8000000, 0xc },
71 { 10000000, 0x6 },
72 { 12000000, 0x9 },
73 { 14000000, 0x7 },
74 { 16000000, 0x10 },
75 { 20000000, 0xa },
76 { 24000000, 0xd },
77 { 28000000, 0xb },
78 { 32000000, 0x14 },
79 { 40000000, 0xe },
80 { 48000000, 0x11 },
81 { 56000000, 0xf },
82 { 64000000, 0x18 },
83 { 80000000, 0x12 },
84 { 96000000, 0x15 },
85 { 112000000, 0x13 },
86 { 128000000, 0x1c },
87 };
88
89 struct ds1wm_data {
90 void __iomem *map;
91 int bus_shift; /* # of shifts to calc register offsets */
92 struct platform_device *pdev;
93 const struct mfd_cell *cell;
94 int irq;
95 int active_high;
96 int slave_present;
97 void *reset_complete;
98 void *read_complete;
99 void *write_complete;
100 u8 read_byte; /* last byte received */
101 };
102
ds1wm_write_register(struct ds1wm_data * ds1wm_data,u32 reg,u8 val)103 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
104 u8 val)
105 {
106 __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
107 }
108
ds1wm_read_register(struct ds1wm_data * ds1wm_data,u32 reg)109 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
110 {
111 return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
112 }
113
114
ds1wm_isr(int isr,void * data)115 static irqreturn_t ds1wm_isr(int isr, void *data)
116 {
117 struct ds1wm_data *ds1wm_data = data;
118 u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
119
120 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
121
122 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
123 complete(ds1wm_data->reset_complete);
124
125 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
126 complete(ds1wm_data->write_complete);
127
128 if (intr & DS1WM_INT_RBF) {
129 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
130 DS1WM_DATA);
131 if (ds1wm_data->read_complete)
132 complete(ds1wm_data->read_complete);
133 }
134
135 return IRQ_HANDLED;
136 }
137
ds1wm_reset(struct ds1wm_data * ds1wm_data)138 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
139 {
140 unsigned long timeleft;
141 DECLARE_COMPLETION_ONSTACK(reset_done);
142
143 ds1wm_data->reset_complete = &reset_done;
144
145 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
146 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
147
148 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
149
150 timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
151 ds1wm_data->reset_complete = NULL;
152 if (!timeleft) {
153 dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
154 return 1;
155 }
156
157 /* Wait for the end of the reset. According to the specs, the time
158 * from when the interrupt is asserted to the end of the reset is:
159 * tRSTH - tPDH - tPDL - tPDI
160 * 625 us - 60 us - 240 us - 100 ns = 324.9 us
161 *
162 * We'll wait a bit longer just to be sure.
163 * Was udelay(500), but if it is going to busywait the cpu that long,
164 * might as well come back later.
165 */
166 msleep(1);
167
168 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
169 DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
170 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
171
172 if (!ds1wm_data->slave_present) {
173 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
174 return 1;
175 }
176
177 return 0;
178 }
179
ds1wm_write(struct ds1wm_data * ds1wm_data,u8 data)180 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
181 {
182 DECLARE_COMPLETION_ONSTACK(write_done);
183 ds1wm_data->write_complete = &write_done;
184
185 ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
186
187 wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
188 ds1wm_data->write_complete = NULL;
189
190 return 0;
191 }
192
ds1wm_read(struct ds1wm_data * ds1wm_data,unsigned char write_data)193 static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
194 {
195 DECLARE_COMPLETION_ONSTACK(read_done);
196 ds1wm_data->read_complete = &read_done;
197
198 ds1wm_write(ds1wm_data, write_data);
199 wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
200 ds1wm_data->read_complete = NULL;
201
202 return ds1wm_data->read_byte;
203 }
204
ds1wm_find_divisor(int gclk)205 static int ds1wm_find_divisor(int gclk)
206 {
207 int i;
208
209 for (i = 0; i < ARRAY_SIZE(freq); i++)
210 if (gclk <= freq[i].freq)
211 return freq[i].divisor;
212
213 return 0;
214 }
215
ds1wm_up(struct ds1wm_data * ds1wm_data)216 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
217 {
218 int divisor;
219 struct ds1wm_driver_data *plat = mfd_get_data(ds1wm_data->pdev);
220
221 if (ds1wm_data->cell->enable)
222 ds1wm_data->cell->enable(ds1wm_data->pdev);
223
224 divisor = ds1wm_find_divisor(plat->clock_rate);
225 if (divisor == 0) {
226 dev_err(&ds1wm_data->pdev->dev,
227 "no suitable divisor for %dHz clock\n",
228 plat->clock_rate);
229 return;
230 }
231 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
232
233 /* Let the w1 clock stabilize. */
234 msleep(1);
235
236 ds1wm_reset(ds1wm_data);
237 }
238
ds1wm_down(struct ds1wm_data * ds1wm_data)239 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
240 {
241 ds1wm_reset(ds1wm_data);
242
243 /* Disable interrupts. */
244 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
245 ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
246
247 if (ds1wm_data->cell->disable)
248 ds1wm_data->cell->disable(ds1wm_data->pdev);
249 }
250
251 /* --------------------------------------------------------------------- */
252 /* w1 methods */
253
ds1wm_read_byte(void * data)254 static u8 ds1wm_read_byte(void *data)
255 {
256 struct ds1wm_data *ds1wm_data = data;
257
258 return ds1wm_read(ds1wm_data, 0xff);
259 }
260
ds1wm_write_byte(void * data,u8 byte)261 static void ds1wm_write_byte(void *data, u8 byte)
262 {
263 struct ds1wm_data *ds1wm_data = data;
264
265 ds1wm_write(ds1wm_data, byte);
266 }
267
ds1wm_reset_bus(void * data)268 static u8 ds1wm_reset_bus(void *data)
269 {
270 struct ds1wm_data *ds1wm_data = data;
271
272 ds1wm_reset(ds1wm_data);
273
274 return 0;
275 }
276
ds1wm_search(void * data,struct w1_master * master_dev,u8 search_type,w1_slave_found_callback slave_found)277 static void ds1wm_search(void *data, struct w1_master *master_dev,
278 u8 search_type, w1_slave_found_callback slave_found)
279 {
280 struct ds1wm_data *ds1wm_data = data;
281 int i;
282 unsigned long long rom_id;
283
284 /* XXX We need to iterate for multiple devices per the DS1WM docs.
285 * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
286 if (ds1wm_reset(ds1wm_data))
287 return;
288
289 ds1wm_write(ds1wm_data, search_type);
290 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
291
292 for (rom_id = 0, i = 0; i < 16; i++) {
293
294 unsigned char resp, r, d;
295
296 resp = ds1wm_read(ds1wm_data, 0x00);
297
298 r = ((resp & 0x02) >> 1) |
299 ((resp & 0x08) >> 2) |
300 ((resp & 0x20) >> 3) |
301 ((resp & 0x80) >> 4);
302
303 d = ((resp & 0x01) >> 0) |
304 ((resp & 0x04) >> 1) |
305 ((resp & 0x10) >> 2) |
306 ((resp & 0x40) >> 3);
307
308 rom_id |= (unsigned long long) r << (i * 4);
309
310 }
311 dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
312
313 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
314 ds1wm_reset(ds1wm_data);
315
316 slave_found(master_dev, rom_id);
317 }
318
319 /* --------------------------------------------------------------------- */
320
321 static struct w1_bus_master ds1wm_master = {
322 .read_byte = ds1wm_read_byte,
323 .write_byte = ds1wm_write_byte,
324 .reset_bus = ds1wm_reset_bus,
325 .search = ds1wm_search,
326 };
327
ds1wm_probe(struct platform_device * pdev)328 static int ds1wm_probe(struct platform_device *pdev)
329 {
330 struct ds1wm_data *ds1wm_data;
331 struct ds1wm_driver_data *plat;
332 struct resource *res;
333 int ret;
334
335 if (!pdev)
336 return -ENODEV;
337
338 ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
339 if (!ds1wm_data)
340 return -ENOMEM;
341
342 platform_set_drvdata(pdev, ds1wm_data);
343
344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
345 if (!res) {
346 ret = -ENXIO;
347 goto err0;
348 }
349 ds1wm_data->map = ioremap(res->start, resource_size(res));
350 if (!ds1wm_data->map) {
351 ret = -ENOMEM;
352 goto err0;
353 }
354 plat = mfd_get_data(pdev);
355
356 /* calculate bus shift from mem resource */
357 ds1wm_data->bus_shift = resource_size(res) >> 3;
358
359 ds1wm_data->pdev = pdev;
360 ds1wm_data->cell = mfd_get_cell(pdev);
361
362 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
363 if (!res) {
364 ret = -ENXIO;
365 goto err1;
366 }
367 ds1wm_data->irq = res->start;
368 ds1wm_data->active_high = plat->active_high;
369
370 if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
371 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
372 if (res->flags & IORESOURCE_IRQ_LOWEDGE)
373 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
374
375 ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
376 "ds1wm", ds1wm_data);
377 if (ret)
378 goto err1;
379
380 ds1wm_up(ds1wm_data);
381
382 ds1wm_master.data = (void *)ds1wm_data;
383
384 ret = w1_add_master_device(&ds1wm_master);
385 if (ret)
386 goto err2;
387
388 return 0;
389
390 err2:
391 ds1wm_down(ds1wm_data);
392 free_irq(ds1wm_data->irq, ds1wm_data);
393 err1:
394 iounmap(ds1wm_data->map);
395 err0:
396 kfree(ds1wm_data);
397
398 return ret;
399 }
400
401 #ifdef CONFIG_PM
ds1wm_suspend(struct platform_device * pdev,pm_message_t state)402 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
403 {
404 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
405
406 ds1wm_down(ds1wm_data);
407
408 return 0;
409 }
410
ds1wm_resume(struct platform_device * pdev)411 static int ds1wm_resume(struct platform_device *pdev)
412 {
413 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
414
415 ds1wm_up(ds1wm_data);
416
417 return 0;
418 }
419 #else
420 #define ds1wm_suspend NULL
421 #define ds1wm_resume NULL
422 #endif
423
ds1wm_remove(struct platform_device * pdev)424 static int ds1wm_remove(struct platform_device *pdev)
425 {
426 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
427
428 w1_remove_master_device(&ds1wm_master);
429 ds1wm_down(ds1wm_data);
430 free_irq(ds1wm_data->irq, ds1wm_data);
431 iounmap(ds1wm_data->map);
432 kfree(ds1wm_data);
433
434 return 0;
435 }
436
437 static struct platform_driver ds1wm_driver = {
438 .driver = {
439 .name = "ds1wm",
440 },
441 .probe = ds1wm_probe,
442 .remove = ds1wm_remove,
443 .suspend = ds1wm_suspend,
444 .resume = ds1wm_resume
445 };
446
ds1wm_init(void)447 static int __init ds1wm_init(void)
448 {
449 printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
450 return platform_driver_register(&ds1wm_driver);
451 }
452
ds1wm_exit(void)453 static void __exit ds1wm_exit(void)
454 {
455 platform_driver_unregister(&ds1wm_driver);
456 }
457
458 module_init(ds1wm_init);
459 module_exit(ds1wm_exit);
460
461 MODULE_LICENSE("GPL");
462 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
463 "Matt Reimer <mreimer@vpop.net>");
464 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
465