Searched refs:DPLL_VCO_ENABLE (Results 1 – 8 of 8) sorted by relevance
442 if ((temp & DPLL_VCO_ENABLE) == 0) { in psb_intel_crtc_dpms()447 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()451 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()506 if ((temp & DPLL_VCO_ENABLE) != 0) { in psb_intel_crtc_dpms()507 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); in psb_intel_crtc_dpms()694 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()704 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()706 REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()973 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in psb_intel_crtc_restore()975 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in psb_intel_crtc_restore()
133 # define DPLL_VCO_ENABLE (1 << 31) macro
42 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); in i915_pipe_enabled()450 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()452 ~DPLL_VCO_ENABLE); in i915_restore_modeset_reg()519 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()521 ~DPLL_VCO_ENABLE); in i915_restore_modeset_reg()
1076 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pll()1094 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pch_pll()1340 val |= DPLL_VCO_ENABLE; in intel_enable_pll()1377 val &= ~DPLL_VCO_ENABLE; in intel_disable_pll()1404 val |= DPLL_VCO_ENABLE; in intel_enable_pch_pll()1424 val &= ~DPLL_VCO_ENABLE; in intel_disable_pch_pll()4916 dpll |= DPLL_VCO_ENABLE; in intel_crtc_mode_set()4933 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); in intel_crtc_mode_set()
715 #define DPLL_VCO_ENABLE (1 << 31) macro
149 #define DPLL_VCO_ENABLE (1 << 31) macro
1111 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); in intelfbhw_mode_to_hw()1403 tmp &= ~DPLL_VCO_ENABLE; in intelfbhw_program_mode()
1374 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); in intelfb_set_par()