Searched refs:DPLL (Results 1 – 6 of 6) sorted by relevance
95 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
181 int dpll_reg = DPLL(pipe); in intel_dvo_mode_set()
1074 reg = DPLL(pipe); in assert_pll()1338 reg = DPLL(pipe); in intel_enable_pll()1375 reg = DPLL(pipe); in intel_disable_pll()4927 dpll_reg = DPLL(pipe); in intel_crtc_mode_set()5603 u32 dpll = I915_READ(DPLL(pipe)); in intel_crtc_clock_get()5763 int dpll_reg = DPLL(pipe); in intel_increase_pllclock()5803 int dpll_reg = DPLL(pipe); in intel_decrease_pllclock()
714 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) macro
31 - Use DSI DPLL to create DSS FCK244 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
291 present at all (BayCom). It feeds back the output of the DPLL