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Searched refs:DMA5_NEXT_DESC_PTR (Results 1 – 18 of 18) sorted by relevance

/linux-2.6.39/arch/blackfin/mach-bf533/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf527/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf518/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf537/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf538/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf548/
Ddma.c20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
/linux-2.6.39/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h257 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ macro
DcdefBF532.h278 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
279 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
/linux-2.6.39/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h291 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ macro
DcdefBF512.h514 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
515 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
/linux-2.6.39/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h291 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ macro
DcdefBF522.h531 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
532 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
/linux-2.6.39/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h267 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register … macro
DcdefBF534.h493 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
494 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
/linux-2.6.39/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h268 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ macro
DcdefBF538.h616 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
617 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
/linux-2.6.39/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h287 #define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Reg… macro
DcdefBF54x_base.h454 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
455 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)