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Searched refs:DMA1_START_ADDR (Results 1 – 12 of 12) sorted by relevance

/linux-2.6.39/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h202 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ macro
DcdefBF532.h172 #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
173 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
/linux-2.6.39/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h236 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ macro
DcdefBF512.h408 #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
409 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h236 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ macro
DcdefBF522.h425 #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h212 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register … macro
DcdefBF534.h387 #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
388 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
/linux-2.6.39/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h213 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ macro
DcdefBF538.h514 #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
515 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h224 #define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */ macro
DcdefBF54x_base.h340 #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
341 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)