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Searched refs:DMA0_CURR_ADDR (Results 1 – 12 of 12) sorted by relevance

/linux-2.6.39/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h194 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ macro
DcdefBF532.h157 #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
158 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
/linux-2.6.39/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h229 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ macro
DcdefBF512.h393 #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
394 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h229 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ macro
DcdefBF522.h410 #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h205 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register … macro
DcdefBF534.h372 #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
373 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
/linux-2.6.39/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h206 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ macro
DcdefBF538.h502 #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
503 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
/linux-2.6.39/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h215 #define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ macro
DcdefBF54x_base.h325 #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
326 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)