| /linux-2.6.39/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7723.c | 118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7724.c | 153 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
159 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
266 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7343.c | 114 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7366.c | 117 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7757.c | 63 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; enumerator
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-shx3.c | 62 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
116 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7785.c | 66 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7722.c | 120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7786.c | 68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
| /linux-2.6.39/arch/arm/mach-shmobile/ |
| D | clock-sh7377.c | 185 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, enumerator
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
286 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh7367.c | 175 enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B, enumerator
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
277 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
| D | clock-sh73a0.c | 214 enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, enumerator
221 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
|
| D | clock-sh7372.c | 339 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, enumerator
348 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
576 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|