Searched refs:DGT_CLK_CTL_DIV_4 (Results 1 – 1 of 1) sorted by relevance
40 DGT_CLK_CTL_DIV_4 = 3, enumerator228 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); in msm_timer_init()274 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); in local_timer_setup()