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Searched refs:DDRPhaseCtrl2 (Results 1 – 2 of 2) sorted by relevance

/linux-2.6.39/arch/arm/mach-bcmring/include/mach/csp/
DchipcHw_inline.h1558 pChipcHw->DDRPhaseCtrl2 &= in chipcHw_ddrHwPhaseAlignTimeout()
1561 pChipcHw->DDRPhaseCtrl2 |= in chipcHw_ddrHwPhaseAlignTimeout()
1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED; in chipcHw_ddrHwPhaseAlignTimeoutInterruptClear()
1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED; in chipcHw_ddrHwPhaseAlignTimeoutInterruptClear()
1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable()
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; in chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable()
DchipcHw_reg.h88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */ member