1 /************************************************************************ 2 * Include file for TRIZEPS4 SoM and ConXS eval-board 3 * Copyright (c) Jürgen Schindele 4 * 2006 5 ************************************************************************/ 6 7 /* 8 * Includes/Defines 9 */ 10 #ifndef _TRIPEPS4_H_ 11 #define _TRIPEPS4_H_ 12 13 /* physical memory regions */ 14 #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ 15 #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ 16 #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ 17 #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 18 #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 19 20 /* Logic on ConXS-board CSFR register*/ 21 #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) 22 /* Logic on ConXS-board BOCR register*/ 23 #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) 24 /* Logic on ConXS-board IRCR register*/ 25 #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) 26 /* Logic on ConXS-board UPSR register*/ 27 #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) 28 /* Logic on ConXS-board DICR register*/ 29 #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) 30 31 /* virtual memory regions */ 32 #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 33 34 #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ 35 #define TRIZEPS4_CFSR_VIRT 0xF0100000 36 #define TRIZEPS4_BOCR_VIRT 0xF0200000 37 #define TRIZEPS4_DICR_VIRT 0xF0300000 38 #define TRIZEPS4_IRCR_VIRT 0xF0400000 39 #define TRIZEPS4_UPSR_VIRT 0xF0500000 40 41 /* size of flash */ 42 #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ 43 44 /* Ethernet Controller Davicom DM9000 */ 45 #define GPIO_DM9000 101 46 #define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) 47 48 /* UCB1400 audio / TS-controller */ 49 #define GPIO_UCB1400 1 50 #define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) 51 52 /* PCMCIA socket Compact Flash */ 53 #define GPIO_PCD 11 /* PCMCIA Card Detect */ 54 #define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) 55 #define GPIO_PRDY 13 /* READY / nINT */ 56 #define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) 57 58 /* MMC socket */ 59 #define GPIO_MMC_DET 12 60 #define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) 61 62 /* DOC NAND chip */ 63 #define GPIO_DOC_LOCK 94 64 #define GPIO_DOC_IRQ 93 65 #define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ) 66 67 /* SPI interface */ 68 #define GPIO_SPI 53 69 #define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI) 70 71 /* LEDS using tx2 / rx2 */ 72 #define GPIO_SYS_BUSY_LED 46 73 #define GPIO_HEARTBEAT_LED 47 74 75 /* Off-module PIC on ConXS board */ 76 #define GPIO_PIC 0 77 #define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) 78 79 #ifdef CONFIG_MACH_TRIZEPS_CONXS 80 /* for CONXS base board define these registers */ 81 #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 82 #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 83 84 #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 85 #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 86 87 #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 88 #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 89 90 #define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) 91 #define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) 92 93 #ifndef __ASSEMBLY__ CFSR_readw(void)94static inline unsigned short CFSR_readw(void) 95 { 96 /* [Compact Flash Status Register] is read only */ 97 return *((unsigned short *)CFSR_P2V(0x0C000000)); 98 } BCR_writew(unsigned short value)99static inline void BCR_writew(unsigned short value) 100 { 101 /* [Board Control Regsiter] is write only */ 102 *((unsigned short *)BCR_P2V(0x0E000000)) = value; 103 } DCR_writew(unsigned short value)104static inline void DCR_writew(unsigned short value) 105 { 106 /* [Display Control Register] is write only */ 107 *((unsigned short *)DCR_P2V(0x0E000000)) = value; 108 } IRCR_writew(unsigned short value)109static inline void IRCR_writew(unsigned short value) 110 { 111 /* [InfraRed data Control Register] is write only */ 112 *((unsigned short *)IRCR_P2V(0x0E000000)) = value; 113 } 114 #else 115 #define ConXS_CFSR CFSR_P2V(0x0C000000) 116 #define ConXS_BCR BCR_P2V(0x0E000000) 117 #define ConXS_DCR DCR_P2V(0x0F800000) 118 #define ConXS_IRCR IRCR_P2V(0x0F800000) 119 #endif 120 #else 121 /* for whatever baseboard define function registers */ CFSR_readw(void)122static inline unsigned short CFSR_readw(void) 123 { 124 return 0; 125 } BCR_writew(unsigned short value)126static inline void BCR_writew(unsigned short value) 127 { 128 ; 129 } DCR_writew(unsigned short value)130static inline void DCR_writew(unsigned short value) 131 { 132 ; 133 } IRCR_writew(unsigned short value)134static inline void IRCR_writew(unsigned short value) 135 { 136 ; 137 } 138 #endif /* CONFIG_MACH_TRIZEPS_CONXS */ 139 140 #define ConXS_CFSR_BVD_MASK 0x0003 141 #define ConXS_CFSR_BVD1 (1 << 0) 142 #define ConXS_CFSR_BVD2 (1 << 1) 143 #define ConXS_CFSR_VS_MASK 0x000C 144 #define ConXS_CFSR_VS1 (1 << 2) 145 #define ConXS_CFSR_VS2 (1 << 3) 146 #define ConXS_CFSR_VS_5V (0x3 << 2) 147 #define ConXS_CFSR_VS_3V3 0x0 148 149 #define ConXS_BCR_S0_POW_EN0 (1 << 0) 150 #define ConXS_BCR_S0_POW_EN1 (1 << 1) 151 #define ConXS_BCR_L_DISP (1 << 4) 152 #define ConXS_BCR_CF_BUF_EN (1 << 5) 153 #define ConXS_BCR_CF_RESET (1 << 7) 154 #define ConXS_BCR_S0_VCC_3V3 0x1 155 #define ConXS_BCR_S0_VCC_5V0 0x2 156 #define ConXS_BCR_S0_VPP_12V 0x4 157 #define ConXS_BCR_S0_VPP_3V3 0x8 158 159 #define ConXS_IRCR_MODE (1 << 0) 160 #define ConXS_IRCR_SD (1 << 1) 161 162 #endif /* _TRIPEPS4_H_ */ 163