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Searched refs:CLK_ENABLE_ON_INIT (Results 1 – 20 of 20) sorted by relevance

/linux-2.6.39/arch/sh/kernel/cpu/sh4a/
Dclock-sh7723.c72 .flags = CLK_ENABLE_ON_INIT,
94 .flags = CLK_ENABLE_ON_INIT,
124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
[all …]
Dclock-sh7343.c71 .flags = CLK_ENABLE_ON_INIT,
90 .flags = CLK_ENABLE_ON_INIT,
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[all …]
Dclock-sh7366.c71 .flags = CLK_ENABLE_ON_INIT,
93 .flags = CLK_ENABLE_ON_INIT,
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
[all …]
Dclock-sh7724.c77 .flags = CLK_ENABLE_ON_INIT,
96 .flags = CLK_ENABLE_ON_INIT,
159 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
160 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
161 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
[all …]
Dclock-sh7722.c71 .flags = CLK_ENABLE_ON_INIT,
93 .flags = CLK_ENABLE_ON_INIT,
123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
Dclock-shx3.c42 .flags = CLK_ENABLE_ON_INIT,
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
Dclock-sh7785.c46 .flags = CLK_ENABLE_ON_INIT,
76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
Dclock-sh7757.c43 .flags = CLK_ENABLE_ON_INIT,
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
Dclock-sh7786.c48 .flags = CLK_ENABLE_ON_INIT,
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
Dclock-sh7763.c82 .flags = CLK_ENABLE_ON_INIT,
Dclock-sh7780.c88 .flags = CLK_ENABLE_ON_INIT,
/linux-2.6.39/arch/sh/kernel/cpu/
Dclock-cpg.c9 .flags = CLK_ENABLE_ON_INIT,
15 .flags = CLK_ENABLE_ON_INIT,
20 .flags = CLK_ENABLE_ON_INIT,
25 .flags = CLK_ENABLE_ON_INIT,
/linux-2.6.39/arch/arm/mach-shmobile/
Dclock-sh73a0.c141 .flags = CLK_ENABLE_ON_INIT,
149 .flags = CLK_ENABLE_ON_INIT,
157 .flags = CLK_ENABLE_ON_INIT,
165 .flags = CLK_ENABLE_ON_INIT,
221 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
222 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
223 [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
224 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
Dclock-sh7377.c119 .flags = CLK_ENABLE_ON_INIT,
146 .flags = CLK_ENABLE_ON_INIT,
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
Dclock-sh7367.c110 .flags = CLK_ENABLE_ON_INIT,
137 .flags = CLK_ENABLE_ON_INIT,
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
Dclock-sh7372.c132 .flags = CLK_ENABLE_ON_INIT,
139 .flags = CLK_ENABLE_ON_INIT,
348 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
349 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
350 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
351 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
/linux-2.6.39/arch/sh/kernel/cpu/sh4/
Dclock-sh4-202.c49 .flags = CLK_ENABLE_ON_INIT,
64 .flags = CLK_ENABLE_ON_INIT,
140 .flags = CLK_ENABLE_ON_INIT,
/linux-2.6.39/include/linux/
Dsh_clk.h61 #define CLK_ENABLE_ON_INIT (1 << 0) macro
/linux-2.6.39/drivers/sh/clk/
Dcpg.c237 if (parent->flags & CLK_ENABLE_ON_INIT) in sh_clk_div4_set_parent()
Dcore.c448 if (clkp->flags & CLK_ENABLE_ON_INIT) in clk_enable_init_clocks()