Searched refs:CLKCTRL_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance
35 #define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) macro105 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \110 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \113 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \126 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \130 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \133 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \162 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \179 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \225 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \[all …]
35 #define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) macro88 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); in pll_clk_enable()103 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR); in pll_clk_disable()122 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \137 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \171 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \194 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ in _CLK_GET_RATE()267 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);270 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);273 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);[all …]