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Searched refs:CKSEG1ADDR (Results 1 – 25 of 33) sorted by relevance

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/linux-2.6.39/arch/mips/include/asm/
Dsni.h38 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
44 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
45 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
46 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
47 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
48 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
49 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
50 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
51 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
52 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
[all …]
Daddrspace.h74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro
81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
Dbarrier.h113 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
/linux-2.6.39/arch/mips/dec/prom/
Didentify.c73 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn01()
81 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); in prom_init_kn230()
90 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); in prom_init_kn02()
99 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn02xa()
100 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn02xa()
109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); in prom_init_kn03()
110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); in prom_init_kn03()
/linux-2.6.39/arch/mips/dec/
Decc-berr.c148 (void *)CKSEG1ADDR(address); in dec_ecc_be_backend()
231 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init()
233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); in dec_kn02_be_init()
234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); in dec_kn02_be_init()
249 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init()
250 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn03_be_init()
252 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); in dec_kn03_be_init()
253 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); in dec_kn03_be_init()
Dkn02xa-berr.c33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_ack()
34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); in dec_kn02xa_be_ack()
44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); in dec_kn02xa_be_backend()
45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); in dec_kn02xa_be_backend()
130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); in dec_kn02xa_be_init()
Dkn02-irq.c34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq()
43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq()
66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs()
Dkn01-berr.c54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack()
67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + in dec_kn01_be_backend()
155 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt()
182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init()
Dint-handler.S29 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
30 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
31 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
Dreset.c16 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); in back_to_prom()
/linux-2.6.39/arch/mips/boot/compressed/
Duart-16550.c13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
/linux-2.6.39/arch/mips/lib/
Duncached.c47 usp = CKSEG1ADDR(sp); in run_uncached()
59 ufunc = CKSEG1ADDR(lfunc); in run_uncached()
/linux-2.6.39/drivers/mtd/devices/
Dms02-nv.c100 ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG)); in ms02nv_probe_one()
101 ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC)); in ms02nv_probe_one()
289 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init()
295 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
/linux-2.6.39/arch/mips/fw/sni/
Dsniprom.c33 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
84 return (void *)CKSEG1ADDR(hwconf); in prom_get_hwconf()
/linux-2.6.39/arch/mips/include/asm/mach-cobalt/
Dmach-gt64120.h25 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
/linux-2.6.39/arch/mips/cobalt/
Dconsole.c9 #define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
Dreset.c19 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
Dpci.c38 .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
Dsetup.c82 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); in plat_mem_setup()
/linux-2.6.39/arch/mips/jz4740/
Dprom.c57 #define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
/linux-2.6.39/drivers/net/
Ddeclance.c1072 dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE); in dec_lance_probe()
1078 dev->mem_start = CKSEG1ADDR(0x00020000); in dec_lance_probe()
1081 esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR); in dec_lance_probe()
1128 dev->mem_start = CKSEG1ADDR(start); in dec_lance_probe()
1157 dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE); in dec_lance_probe()
1158 dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM); in dec_lance_probe()
1160 esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1); in dec_lance_probe()
/linux-2.6.39/arch/mips/pci/
Dops-bonito64.c32 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
Dpci-ip32.c122 .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
/linux-2.6.39/arch/mips/include/asm/mach-powertv/
Dioremap.h153 CKSEG1ADDR(adjusted_start); in plat_ioremap()
/linux-2.6.39/arch/mips/include/asm/dec/
Dprom.h26 #define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)

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